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The Quarterly Review ; March edition, 1825
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| Number | Title | Issue Date |
| 5136500 | Multiple shared memory arrangement wherein multiple processors individually and concurrently access any one of plural memories A memory controller in which a number of local memories are primarily dedicated to the shared use of a number of local processors of a data processing system to increase the efficiency of use of both the processors and memories. A controller is associated... | 08/04/1992 |
| 5036456 | Apparatus for controlling concurrent operations of a system control unit including activity register circuitry In a data processing system having a system controller unit (SCU) which interfaces a plurality of equipments with a memory unit, the SCU determines which of the equipments will be permitted to communicate with the SCU or memory unit in response to a reque... | 07/30/1991 |
| 4695923 | Printed circuit board bolt-on power distribution system A bolt-on configuration of a power distribution system utilizes an apparatus which connects a first element to a second element, the second element having a hole, such that a minimum predetermined force exists at the connection between the first element a... | 09/22/1987 |
| 4680702 | Merge control apparatus for a store into cache of a data processing system A register unit includes means for storing pertinent data relative to a plurality of cache transactions, identifying the zones of an addressed word block which is the subject of the individual transactions. These data are selectively extracted from the re... | 07/14/1987 |
| 4665822 | Squeegee for screen process printers for printing of dielectric and metallic pastes for single and multilayer hybrid circuits A squeegee is utilized in a screen process printer for microcircuits and components thereof. The type is one in which the squeegee and a flat stationary screen are mounted with the squeegee movable and in a wiping action makes contact with the screen so a... | 05/19/1987 |
| 4662067 | Apparatus and method for providing orientation of a coax cable having a ground termination bar A connector for providing electrical connections for a coax cable harness, the coax cable harness including a plurality of coax cables, each coax cable having a wire encased in a dielectric and having a drain wire. The connector comprises an insulation di... | 05/05/1987 |
| 4649539 | Apparatus providing improved diagnosability An apparatus for storing information contained in a selected digital data signal comprises a selector. A first input terminal receives an operational digital data signal when the apparatus is operating in a normal mode, a second input terminal receives a ... | 03/10/1987 |
| 4628489 | Dual address RAM In a computer system, a memory system has a memory structure and means whereby the smallest memory unit, the RAM chip, may be addressed and accessed twice during each clock cycle.... | 12/09/1986 |
| 4625312 | Test and maintenance method and apparatus for investigation of intermittent faults in a data processing system A test and maintenance system for use with a data processing system comprising a specialized circuit set wherein the circuit set registers can be configured into a serial array, a clock signal distribution system capable of delivering controlled clock sig... | 11/25/1986 |
| 4620274 | Data available indicator for an exhausted operand string The present invention relates to an apparatus for providing a data available indication while inhibiting the reading of operand data beyond the last word of an operand data string. The data available indication operates to enable additional cycles to be g... | 10/28/1986 |
| 4611278 | Wraparound buffer for repetitive decimal numeric operations The present invention relates to the operational control of a digital computer system which includes the digital logic circuitry for temporarily storing results internal to an execution unit. An input unit of the execution, which inputs operand words to t... | 09/09/1986 |
| 4610001 | Write amplifier A write amplifier for a computer memory unit features a first and a second output terminal. The amplifier may be controlled, in the write mode, to provide output signals, on the two output terminals, of one relative polarity or the other in accordance wit... | 09/02/1986 |
| 4608633 | Method for decreasing execution time of numeric instructions The present invention relates to a method within a digital computer system for reading operand data stored in a temporary storage memory in a forward or reverse direction. The method includes loading the temporary storage memory with the first and second ... | 08/26/1986 |
| 4602368 | Dual validity bit arrays An associative memory used to translate a virtual page number (VPN) of a virtual word address to a physical page number (PPN) of a physical word address of a random access memory of a digital computer system is provided with a pair of independently addres... | 07/22/1986 |
| 4598365 | Pipelined decimal character execution unit The present invention relates to an execution unit of a computing system which executes data manipulation type instructions and arithmetic type instructions on data words having a plurality of decimal character-type data formats. The pipelined execution u... | 07/01/1986 |
| 4598359 | Apparatus for forward or reverse reading of multiple variable length operands The present invention relates to an operational control of a digital computer system for reading operand data stored in a temporary storage memory in a forward or reverse direction. The present invention includes an adder for adding the current read addre... | 07/01/1986 |
| 4597044 | Apparatus and method for providing a composite descriptor in a data processing system In a data processing system including a central processing unit capable of operation with a plurality of operating systems, a VMSM unit is described for producing a composite decor descriptor from a plurality of possible decor descriptor formats. The VMSM... | 06/24/1986 |
| 4594659 | Method and apparatus for prefetching instructions for a central execution pipeline unit Method and apparatus for prefetching instructions for a pipelined central processor unit for a general purpose digital data processing system. A table is maintained for purposes of predicting the target addresses of transfer and indirect instructions base... | 06/10/1986 |
| 4593349 | Power sequencer A peripheral power control sequencer incorporates a microcomputer to control the sequencing of the powering of a plurality of peripheral control units. The terminals of the input/output ports of the microcomputer are time-shared to accommodate the several... | 06/03/1986 |
| 4583199 | Apparatus for aligning and packing a first operand into a second operand of a different character size The present invention relates to an alignment network for aligning data words having a plurality of data word formats. A plurality of shifters are utilized, each shifter utilized to shift the corresponding bit of each character. When the output data word ... | 04/15/1986 |
| 4581738 | Test and maintenance method and apparatus for a data processing system A test and maintenance system for use with a data processing system comprising a specialized circuit set wherein the circuit set registers can be configured into a serial array, a clock signal distribution system capable of delivering controlled clock sig... | 04/08/1986 |
| 4575795 | Apparatus for detecting a predetermined character of a data string The present invention relates to digital logic circuitry for detecting a predetermined character of a data string for operand data stored in a temporary storage memory or while the data is being loaded into the temporary storage memory, wherein the data s... | 03/11/1986 |
| 4573116 | Multiword data register array having simultaneous read-write capability An improved multiword data register array which features RAM technology to provide a greater memory capacity in a smaller space than a conventional register arrays. Whereas RAM technology does not ordinarily include the capability of simultaneously readin... | 02/25/1986 |
| 4569009 | Switching regulator having a selectable gain amplifier for providing a selectively alterable output voltage A power supply for providing a selectable predetermined regulated output voltage. A switching regulator circuit provides the conversion of an input voltage to a DC output voltage and a control circuit, which senses the output voltage, controls the convers... | 02/04/1986 |
| 4567571 | Memory control for refreshing in a step mode In a computer system, there is included a memory unit which includes a volatile memory store, and a memory control circuit connected with the memory unit thereby permitting the computer system to be operated in a step mode, the memory control circuit comp... | 01/28/1986 |
| 4567593 | Apparatus for verification of a signal transfer in a preselected path in a data processing system A specialized circuit set is included in a data processing system wherein the circuit set registers can be configured into a serial array. A clock signal distribution system delivers controlled clock signals to selected serial arrays. A maintenance data p... | 01/28/1986 |
| 4561053 | Input/output multiplexer for a data processing system In an input/output multiplexer of a data processing unit, a plurality of components, capable of independent activity, provide for the simultaneous execution of a multiplicity of operations involving the exchange of signal groups between a central subsyste... | 12/24/1985 |
| 4553201 | Decoupling apparatus for verification of a processor independent from an associated data processing system In a data processing system having a plurality of CPUs, each CPU is operatively connected to other portions of the data processing system through a system interface unit. The CPU includes a cache memory, an execution unit, and a control unit. Further, eac... | 11/12/1985 |
| 4553053 | Sense amplifier A sense amplifier for a computer memory includes a plural stage differential amplifier. The first stage of the differential amplifier includes an input emitter follower connected to the input of the first stage differential pair. A negative feedback loop ... | 11/12/1985 |
| 4551799 | Verification of real page numbers of stack stored prefetched instructions from instruction cache A cache memory includes a dual or two part cache with one part of the cache being primarily designated for instruction data while the other is primarily designated for operand data, but not exclusively. For a maximum speed of operation, the two parts of t... | 11/05/1985 |
| 4538237 | Method and apparatus for calculating the residue of a binary number Method and apparatus for calculating the residue of a binary number of "n" bits with respect to a given check base m where m=2b -1. The binary number is partitioned into segments, each of b bits starting with the least significant bit. If n is ... | 08/27/1985 |
| 4538238 | Method and apparatus for calculating the residue of a signed binary number Method and apparatus for calculating the residue of a signed binary number of "n" bits with respect to a given check base m where m=2b -1. The bits of the binary number excluding the sign bit are partitioned into number segments, each of b bits... | 08/27/1985 |
| 4530052 | Apparatus and method for a data processing unit sharing a plurality of operating systems Apparatus and method for a supervisor for data processing system capable of utilizing a plurality of operating systems. The supervisor includes apparatus for identifying a condition in the data processing system requiring a different operating system. A r... | 07/16/1985 |
| 4527238 | Cache with independent addressable data and directory arrays Cache memory includes a dual or two part cache with one part of the cache being primarily designated for instruction data while the other is primarily designated for operand data, but not exclusively. For a maximum speed of operation, the two parts of the... | 07/02/1985 |
| 4525714 | Programmable logic array with test capability in the unprogrammed state A programmable circuit array comprises an input buffer adapted to receive a plurality of input signals for outputting equivalent input signals and inverted input signals. A programmable product array receives the equivalent input signals and the inverted ... | 06/25/1985 |
| 4525777 | Split-cycle cache system with SCU controlled cache clearing during cache store access period In a cache memory unit including a cache directory identifying signal groups stored in an associated cache storage unit, apparatus and method are disclosed for searching the cache directory during a second portion of the cache memory cycle when the cache ... | 06/25/1985 |
| 4521692 | Motor generator shutdown circuit for extended ridethrough This invention relates to device for detecting a threshold value of the frequency of an input signal. A gate signal is generated from the input signal, whose period has a relationship to the frequency of the input signal. A counter counts pulses from an o... | 06/04/1985 |
| 4521850 | Instruction buffer associated with a cache memory unit Apparatus and method for providing an improved instruction buffer associated with a cache memory unit. The instruction buffer is utilized to transmit to the control unit of the central processing unit a requested sequence of data groups. In the current in... | 06/04/1985 |
| 4521851 | Central processor A central processor for a general-purpose digital data processing system. The processor has a pair of caches, an operand cache for operands and an instruction cache for instructions, as well as a plurality of execution units, where each execution unit exe... | 06/04/1985 |
| 4514815 | Computerized system and method of material control A system and method for material control to allow tracking and prevent diversion of articles within the system having a computer connected to a visual display, a keyboard, and printer. The computer is also connected to an OCR device for reading labels ass... | 04/30/1985 |
