Assignee: HaL Computer Systems, Inc.

Location: Campbell, CA
No. of patents: 26

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Number	Title	Issue Date
5751985	Processor structure and method for tracking instruction status to maintain precise state Apparatus and method provide for tracking and maintaining precise state by assigning a unique identification tag to each instruction at the time of issue, associating the tag with a storage location in a first active instruction data structure, updating t...	05/12/1998
5689673	Apparatus and method for controlling instruction flow by using a matrix of transmission gates in super-scaler microprocessor and selectively delaying microprocessor instruction execution based on resource availability An instruction flow control circuit controls the selection and execution of instruction signals in a microprocessor having multiple execution units that can execute plural instructions at one time. The instruction flow control circuit compares a number of...	11/18/1997
5687353	Merging data using a merge code from a look-up table and performing ECC generation on the merged data A system and method providing ECC protection for all data block sizes for which a computer system supports store (ST) accesses includes an access control logic unit which converts store accesses for small data block (ࣘ64-bits) into read-modify (merge)-w...	11/11/1997
5680566	Lookaside buffer for inputting multiple address translations in a computer system A method and apparatus for performing address translation in a computer system supporting virtual memory by searching a translation lookaside buffer (TLB) and, possibly, a translation table held in memory and implemented as a B-tree data structure. The TL...	10/21/1997
5673426	Processor structure and method for tracking floating-point exceptions An out of program control order execution data processor that comprises an issue unit, execution means, a floating point exception unit a precise state unit, a floating point status register, and writing means. The issue unit issues instructions in progra...	09/30/1997
5671151	Self-timed logic circuit having zero-latency overhead and method for designing same Asynchronous combinatorial logic apparatus and method are provided that propagate data through a logic array at the speed of a raw combinational logic array and generate a functional output signal. The apparatus and method provide a minimum expected value...	09/23/1997
5652580	Method and apparatus for detecting duplicate entries in a look-up table A method and apparatus detects whether more than one object has been selected from a set of objects. A unique code and an error code is coupled to objects in the set. At least one object is selected and the unique codes from the selected object are logica...	07/29/1997
5649136	Processor structure and method for maintaining and restoring precise state at any instruction boundary A high-performance processor is disclosed with structure and methods for: (1) aggressively scheduling long latency instructions including load/store instructions while maintaining precise state; (2) maintaining and restoring precise state at any instructi...	07/15/1997
5644742	Processor structure and method for a time-out checkpoint Time-out checkpoints are formed based on a predetermined time-out condition or interval since the last checkpoint was formed rather than forming a checkpoint to store current processor state based merely on decoded Instruction attributes. Such time-out co...	07/01/1997
5644604	Digital phase selector system and method A system and method for transferring data between clock domains operating at substantially the same frequency continuously compares the relationship between a delayed data phase signal driven by a non-delayed source domain clock and a data phase signal sa...	07/01/1997
5638312	Method and apparatus for generating a zero bit status flag in a microprocessor A method and apparatus for generating a zero flag (z-flag) status signal in a microprocessor includes a z-flag signal generator that generates a z-flag signal from unaligned data simultaneous to the load alignment of such data. The z-flag generator first ...	06/10/1997
5632028	Hardware support for fast software emulation of unimplemented instructions A system and method provides hardware support for fast software emulation of unimplemented instructions using issue trap logic that determines the instruction type and parameter fields of an unimplemented instruction when an exception is triggered and use...	05/20/1997
5615161	Clocked sense amplifier with positive source feedback A differential sense amplifier includes positive feedback cross coupling to control operation in one mode as a differential sense amplifier and in another mode as a latch to control a data-latching load. Circuit nodes are precharged and equalized in respo...	03/25/1997
5533035	Error detection and correction method and apparatus A method and apparatus are disclosed for detecting and correcting errors in the data stored within the entries of a memory table. Each time data is entered into the memory table, an error code generator generates a corresponding error code using the data....	07/02/1996
5528553	Method and apparatus for testing random access memory A memory is tested by subjecting the memory to three phases of testing. In the first phase, a first address in the memory is initialized by writing an initial set of data to the address. Then data is read from the address just written to and this data is ...	06/18/1996
5513132	Zero latency overhead self-timed iterative logic structure and method A novel third phase of CMOS domino logic is identified and used in the logic system of the present invention to store data. The use of this third phase in addition to the normally used precharge and logic evaluation phases, provides a logic structure of c...	04/30/1996
5509038	Multi-path data synchronizer system and method A system and method for transferring data between clock domains operating at substantially the same frequency continuously compares the phase relationship of the clocks of the two domains and retains the current state of comparison at the start of a trans...	04/16/1996
5469443	Method and apparatus for testing random access memory A memory is tested by subjecting the memory to three phases of testing. In the first phase, a first address in the memory is initialized by writing an initial set of data to the address. Then data is read from the address just written to and this data is ...	11/21/1995
5455834	Fault tolerant address translation method and system A method and system are disclosed wherein error detection codes are used for detecting and handling hardware errors in a memory table. Before each address and associated data are entered into the memory table, an error detection code is generated for both...	10/03/1995
5454094	Method and apparatus for detecting multiple matches in a content addressable memory A circuit and method for detecting multiple matches or hits in a content addressable memory (CAM) are disclosed. The circuit includes a logarithmic index generator or encoder, and a converter which provides a unary signal to an attached random access memo...	09/26/1995
5347482	Multiplier tree using nine-to-three adders A multiplier tree sums the partial products of a multiplication operation, employing a regular hierarchical arrangement of bit adders that accept nine initial inputs and a carry input and produce three outputs and a carry output. The regularity of the str...	09/13/1994
5347481	Method and apparatus for multiplying denormalized binary floating point numbers without additional delay A structure of logic gates, partial product circuits, and a multiplier tree is described for multiplying of two operands which may contain denormalized numbers in the same amount of time as needed to multiply normalized numbers. The generation of the most...	09/13/1994
5329476	Method and apparatus for early quotient completion in arithmetic division Apparatus and methods for early quotient completion in arithmetic division include a quotient digit generator, one or more asynchronous shift registers and a remainder comparison block. As quotient digits are generated, each digit is transferred to a diff...	07/12/1994
5319590	Apparatus for storing "Don't Care" in a content addressable memory cell A content addressable memory cell is able to store a state representing "Don't Care", by storing two bits of data. The "Don't Care" state is indicated by storing two identical bits corresponding to a predetermined value, so that the cell indicates a match...	06/07/1994
5266849	Tri state buffer circuit for dual power system A CMOS tri-state buffer circuit transfers digital signals between a first digital circuit system operating at 3.3 Volts and a second system operating at 5 Volts. The buffer circuit receives an active high enable signal and a data signal as inputs to a tri...	11/30/1993
5121003	Zero overhead self-timed iterative logic CMOS domino logic is normally used only in two phases: precharge and logic evaluation. The invention uses a third phase to store data, which allows domino logic gates to be cascaded and pipelined without intervening latches. The inputs to this system must...	06/09/1992

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Assignee: HaL Computer Systems, Inc.