A coffin, for allowing inclination for display of a deceased person in a natural position.
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| Number | Title | Issue Date |
| 8143927 | Pulse control device A pulse control device is maintained with a constant pulse width corresponding to a change of process or temperature. The pulse control device comprises a fuse set for selectively outputting a delay increase signal and a delay decrease signal that have a different s... | 03/27/2012 |
| 7843219 | XOR logic circuit An XOR logic circuit includes a first transfer unit configured to transfer a logic high level data to an output terminal in response to data applied to first and second input terminals; a multiplexing unit configured to output a power voltage or a ground voltage in ... | 11/30/2010 |
| 7825699 | Receiver circuit having compensated offset voltage A receiver circuit includes an offset control signal generating unit that outputs a plurality of offset control signals using an offset voltage. A sense amplifier receives a first current and a second current generated on the basis of an up input signal and a down i... | 11/02/2010 |
| 7811929 | Method for forming dual damascene pattern A method for forming a dual damascene pattern includes preparing a multi-functional hard mask composition including a silicon resin as a base resin; forming a deposition structure including a self-arrangement contact insulation film, a first dielectric film, an etch... | 10/12/2010 |
| 7782698 | Refresh signal generator of semiconductor memory device A refresh signal generator generates an internal refresh signal to conduct a refresh with an interval controlled based on PVT fluctuations. The refresh signal generator includes a temperature sensing unit for sensing an internal temperature and activating a correspo... | 08/24/2010 |
| 7782685 | Semiconductor device and operating method thereof A semiconductor device includes a pad configured to receive a data strobe signal, and a path selector configured to output the data strobe signal through a corresponding input path during a normal operation, and to output the data strobe signal through a plurality o... | 08/24/2010 |
| 7782684 | Semiconductor memory device operating in a test mode and method for driving the same A semiconductor memory device is capable of controlling a tRCD (RAS to CAS Delay) time regardless of an address input timing during a test operation of the semiconductor memory device. The semiconductor memory device includes a column address strobe pulse generator ... | 08/24/2010 |
| 7781336 | Semiconductor device including ruthenium electrode and method for fabricating the same A semiconductor device includes a semiconductor substrate, an insulation pattern on the semiconductor substrate, and an etch stop layer on the insulating pattern, the insulation pattern and the etch stop layer defining a contact hole that exposes the substrate, a fi... | 08/24/2010 |
| 7778102 | Semiconductor memory device The present invention provides a semiconductor memory device that can reduce unnecessary current consumption, as banks not accessing data maintain an inactivation state and do not receive an input address. A semiconductor memory device includes a plurality of banks ... | 08/17/2010 |
| 7778095 | Semiconductor memory device and method for driving the same A semiconductor memory device includes a delay locked loop (DLL) unit configured to generate a plurality of DLL clocks, each having a different phase according to delay values predefined by a DLL operation; a data output buffering unit configured to output data in r... | 08/17/2010 |
| 7773709 | Semiconductor memory device and method for operating the same A semiconductor memory device includes an aligning signal generator, a data aligning unit, a data transmitting controller and a data transmitter. The aligning signal generator receives a data strobe signal to output aligning signals. The data aligning unit aligns a ... | 08/10/2010 |
| 7773448 | Semiconductor memory device A semiconductor memory device having multiple banks each including multiple memory blocks arranged in column and row directions. The memory blocks are divided into multiple memory block groups each sharing a corresponding column select signal. The memory blocks belo... | 08/10/2010 |
| 7773440 | ZQ calibration controller and method for ZQ calibration A ZQ calibration circuit performs a ZQ calibration additionally in an initial operation of a semiconductor memory device. The ZQ calibration controller of the ZQ calibration circuit includes a first signal generator, a second signal generator, and a control unit. Th... | 08/10/2010 |
| 7772899 | Delay locked loop and operating method thereof A delay locked loop (DLL) includes a delay-locking unit configured to generate first and second delay clocks corresponding to first and second clock edges of a reference clock for achieving a delay-locking; a phase detection unit configured to detect a phase differe... | 08/10/2010 |
| 7772878 | Parallel resistor circuit, on-die termination device having the same, and semiconductor memory device having the on-die termination device A parallel resistor circuit that can reduce an error of a resistance value, an on-die termination having the same, and a semiconductor device having the on-die termination device. The semiconductor memory device includes a calibration circuit configured to pull up o... | 08/10/2010 |
| 7772132 | Method for forming tetragonal zirconium oxide layer and method for fabricating capacitor having the same A method for forming a zirconium oxide (ZrO2) layer on a substrate in a chamber includes controlling a temperature of the substrate; and repeating a unit cycle of an atomic layer deposition (ALD) method. The unit cycle includes supplying a zirconium (Zr) ... | 08/10/2010 |
| 7772082 | Capacitor of semiconductor device and method of fabricating the same A method of fabricating a semiconductor device includes forming a buffer insulating film over a semiconductor substrate including a conductive pattern. The buffer insulating film is etched using a storage node mask to form a buffer insulating pattern exposing the co... | 08/10/2010 |
| 7768843 | Semiconductor memory device for generating back-BIAS voltage with variable driving force A semiconductor memory device is capable of maintaining a predetermined back-bias voltage level regardless of operation modes of the semiconductor memory device, by generating a back-bias voltage with driving force changed according to the operation modes. The semic... | 08/03/2010 |
| 7768327 | Delay locked loop of semiconductor device and method for driving the same A delay locked loop (DLL) of a semiconductor device includes: a first delay line for delaying a first clock signal in synchronization with a first edge of an external clock signal to output a first delayed clock signal; a second delay line for delaying a second cloc... | 08/03/2010 |
| 7768053 | Semiconductor device with asymmetric transistor and method for fabricating the same A semiconductor device with an asymmetric transistor and a method for fabricating the same are provided. The semiconductor device includes: a substrate having a plurality of first active regions, at least one second active region, and a plurality of device isolation... | 08/03/2010 |
| 7764112 | Internal voltage discharge circuit and its control method An internal voltage discharge circuit includes a differential comparator for differentially comparing a reference voltage with a feedback voltage to generate a discharge control voltage, a level detector for detecting a level of external power supply voltage and a d... | 07/27/2010 |
| 7764110 | Internal voltage generating circuit of semiconductor device An internal voltage generating circuit of a semiconductor device includes a first voltage driver configured to pull up an internal voltage terminal during a period where a level of the internal voltage terminal is lower than a target level, and a second voltage driv... | 07/27/2010 |
| 7764106 | Semiconductor device A semiconductor device is capable of stably maintaining a voltage level of a shield line, even when a voltage level of an adjacent line is varied. The semiconductor device includes normal lines arranged for transfer of signals, a shield line arranged adjacently to t... | 07/27/2010 |
| 7760002 | Clock generating circuit and clock generating method thereof A clock generating circuit, including a pulse generating unit to generate a plurality of pulse signals based on a reference clock, the pulse signals each having the same period, a phase difference between the adjacent pulse signals being a first phase difference; an... | 07/20/2010 |
| 7755393 | Output driver for use in semiconductor device An output driver for use in a semiconductor device includes a first pre-drive unit, a second pre-drive unit, and a main drive unit. The first pre-drive unit generates a pull-up drive control signal based on a data signal. The pull-up drive control signal swings betw... | 07/13/2010 |
| 7755390 | XOR logic circuit An XOR logic circuit includes a first transfer unit configured to transfer a logic high level data to an output terminal in response to data applied to first and second input terminals; a multiplexing unit configured to output a power voltage or a ground voltage in ... | 07/13/2010 |
| 7755383 | Calibration circuit, semiconductor memory device including the same, and operating method of the calibration circuit Calibration circuit, semiconductor memory device including the same, and operation method of the calibration circuit includes a calibration unit configured to generate a calibration code for controlling a termination resistance value, a calibration control unit conf... | 07/13/2010 |
| 7754577 | Method for fabricating capacitor A method for fabricating a capacitor includes: forming a storage node contact plug over a substrate; forming an insulation layer having an opening exposing a surface of the storage node contact plug over the storage contact plug; forming a conductive layer for a sto... | 07/13/2010 |
| 7749895 | Capacitor of semiconductor device and method for fabricating the same A method for fabricating a semiconductor device includes forming an interlayer insulating film over a semiconductor substrate. The interlayer insulating film is selectively etched to form a hole defining a storage node region. A lower electrode is formed in the hole... | 07/06/2010 |
| 7749843 | Method for fabricating semiconductor device with bulb-shaped recess gate A method for fabricating a semiconductor device with a bulb-shaped recess gate pattern is provided. The method includes forming a plurality of oxide layers over a substrate; forming a silicon layer to cover the oxide layers; forming a mask over the silicon layer; et... | 07/06/2010 |
| 7746723 | Semiconductor memory device and driving method thereof A semiconductor memory device includes: a variable delay for delaying a delay locked loop (DLL) clock by a predetermined delay time to output a delayed DLL clock; an output driver for outputting data and data strobe signal in response to the delayed DLL clock; and a... | 06/29/2010 |
| 7746714 | Semiconductor memory device having bit-line sense amplifier A semiconductor memory device including a bit-line sense amplifier is not affected by variation in manufacturing process and has a stable driving scheme. The semiconductor memory device includes: a unit memory cell for storing a data; a sense amplification unit incl... | 06/29/2010 |
| 7742349 | Semiconductor memory device A circuit can control a bit rate of information output from a multi-purpose register (MPR) of a semiconductor memory device in a test mode, thereby reducing current consumption for outputting information in a multi-purpose register (MPR). The semiconductor memory de... | 06/22/2010 |
| 7741891 | Delay locked loop circuit A delay locked loop increases an operation margin of a delay locked loop by using an output clock having more advanced phase than a DLL output clock. A clock delay compensation block receives an external clock signal to thereby generate a first multi clock and a sec... | 06/22/2010 |
| 7741170 | Dielectric structure in nonvolatile memory device and method for fabricating the same A dielectric structure in a nonvolatile memory device and a method for fabricating the same are provided. The dielectric structure includes: a first oxide layer; a first high-k dielectric film formed on the first oxide layer, wherein the first high-k dielectric film... | 06/22/2010 |
| 7738307 | Data transmission device in semiconductor memory device A semiconductor device is capable of minimizing data skew among respective data which are transmitted to a receiver through respective data lines. The semiconductor device includes a synchronization unit connected to at least one portion of the respective data lines... | 06/15/2010 |
| 7737768 | Internal voltage generator An internal voltage generator of a semiconductor memory device generates an internal voltage sensitive to a change in a temperature. The internal voltage generator includes a reference voltage generator, an internal voltage detecting unit and an internal voltage pum... | 06/15/2010 |
| 7737744 | Register controlled delay locked loop circuit A register controlled delay locked loop (DLL) circuit, including: a phase comparator configured to compare phases of a source clock and a feedback clock with each other, and a clock delay circuit configured to delay a phase of an internal clock synchronized with a c... | 06/15/2010 |
| 7737712 | Probe-testing device and method of semiconductor device A probe-testing device includes probe tips configured to apply inputs to pads of a semiconductor chip, wherein one of the probe tips is connected to a calibration pad for impedance adjustment and a calibration resistor is connected thereto. ... | 06/15/2010 |
| 7733736 | Semiconductor memory device for driving a word line A semiconductor memory device for driving a word line is provided. The enabling timing of a word line is advanced using a block information signal that contains no redundancy information, thereby improving a RAS to CAS delay (tRCD). A sub word line driving enable si... | 06/08/2010 |