Assignee: Grace Semiconductor Manufacturing Corporation

Location: Shanghai, CN
No. of patents: 21

Number	Title	Issue Date
7816018	Organic electroluminescent materials and organic electroluminescent device using the same An organic electroluminescent material having the formula and an organic electroluminescent material used for electroluminescent devices is characterized by emission with a high luminance, high illuminant efficiency, low dr...	10/19/2010
7452639	Photomask with photoresist test patterns and pattern inspection method A photomask with photoresist test patterns and pattern inspection method using four test patterns on the photomask to perform the exposure on the first photoresist layer in order to adjust the photomask. The present invention prevents misalignment of the first photo...	11/18/2008
7387948	Structure and method of forming a semiconductor material wafer A structure and method of forming a semiconductor material wafer comprising forming an ingot of semiconductor material. A first dielectric layer is formed on the surface of the ingot, and the surface of the first dielectric layer is larger than the surface of the in...	06/17/2008
7371664	Process for wafer thinning The present invention relates to a process for thinning a semiconductor wafer. Two surfaces of the wafer separately form a surface-bond glue (layer) and a surface protective glue (layer). The thinning process is applied to the wafer before forming the surface protec...	05/13/2008
7338853	High power radio frequency integrated circuit capable of impeding parasitic current loss A high power RF IC capable of impeding parasitic current loss and method of manufacturing the same. First a step of semiconductor front-side processing for the high power RF components that includes inductive components is performed. Afterwards, the backside of semi...	03/04/2008
7332741	Multidirectional leakage path test structure A test structure for testing a multidirectional current leakage path. A first doped region of a first conductivity is in the first well of the first conductivity in a substrate, in which the first doped region has a dopant concentration higher than the first well ha...	02/19/2008
7324382	Current-mode sensing structure used in high-density multiple-port register in logic processing and method for the same A current-mode sensing structure used in a high-density multiple-port register in logic processing and a method for the same are proposed. First, a reference current is defined by a dummy word line of a dummy cell and output. A multiple-port register file cell is th...	01/29/2008
7307016	Method of processing metal surface in dual damascene manufacturing A processing method for the metal surface in a dual damascene manufacturing is applied to a dual damascene semiconductor structure. The dual damascene semiconductor structure has a metal structure and a spin-on-dielectric (SOD) layer formed on the metal structure, w...	12/11/2007
7282417	Ion doping method to form source and drain An ion doping method to form source and drain is disclosed. First form a gate structure and a gate spacer on a semiconductor substrate, and then use dielectric layer having trenches therein to define heavily ion-doped positions and use a Y-shaped polysilicon layer f...	10/16/2007
7280423	Current-mode sensing structure of high-density multiple-port register in embedded flash memory procedure and method for the same A current-mode sensing structure of a high-density multiple-port register in embedded flash memory procedure and a method for the same are proposed. A multiple-port register file cell is used to send out a select signal of “0” or “1”. Based on this select si...	10/09/2007
7221035	Semiconductor structure avoiding poly stringer formation The present invention discloses a semiconductor structure avoiding the poly stringer formation in semiconductor processing. A semiconductor device is divided into a memory cell area and a peripheral portion. A plurality of parallel first isolation devices are positi...	05/22/2007
7192823	Manufacturing method for transistor of electrostatic discharge protection device A manufacturing method for a transistor of an ESD protection device. First, the method forms basic elements on a semiconductor base. Next, a patterned resist layer is used as a mask to perform ion implantation in the emerged drain region so that the dopant can be im...	03/20/2007
7186603	Method of forming notched gate structure A method of forming a notched gate structure comprising a semiconductor substrate having a first oxide layer formed thereon. A first conductive layer is formed on the semiconductor substrate. A portion of the first conductive layer and a portion of the first oxide l...	03/06/2007
7141469	Method of forming poly insulator poly capacitors by using a self-aligned salicide process A method of forming poly insulator poly capacitors by using self-aligned salicide process for mixed mode analog devices. These capacitors are formed in the self-aligned salicide process as stacked poly insulator poly (PIP) capacitors. In the self-aligned salicide pr...	11/28/2006
7084036	Data writing method for mask read only memory A data writing method for mask read only memory using different doses of ion implantations to perform the data writing of Mask Read Only Memory. A semiconductor substrate having a plurality of gate structures is provided. The different ion implantations are performe...	08/01/2006
7022583	Method of forming a shallow trench isolation device to prevent kick effect A method of forming a shallow trench isolation device in order to prevent kick effects comprising a semiconductor structure having a patterned masking layer formed thereon. A shallow trench is formed in the semiconductor structure by using the patterned masking laye...	04/04/2006
7022567	Method of fabricating self-aligned contact structures A method of fabricating self-aligned contact structures comprising providing a semiconductor substrate having at least two conductive structures thereon. The conductive structures are positioned beside the desired self-aligned contact structures having a plurality o...	04/04/2006
7022565	Method of fabricating a trench capacitor of a mixed mode integrated circuit A method of fabricating a trench capacitor of a mixed mode integrated circuit includes forming shallow trench isolation regions for isolating active/passive devices on a semiconductor substrate. The lower electrode layer of the polysilicon layer, the dielectric laye...	04/04/2006
7015149	Simplified dual damascene process A simplified dual damascene process is disclosed. In the dual damascene process, a semiconductor substrate with MOS devices having a first metal layer, an etch stopping layer, and a dielectric layer in sequence are formed thereon. A via is formed on the dielectric l...	03/21/2006
6998868	Test key for bridge and continuity testing A test key for bridging and continuity testing is provided, comprising at least one test unit, which is composed of a first strand and a second strand embedded or non-touching intertwined with each other. The strand comprising a closed hook, a corresponding extensio...	02/14/2006
6968251	Defect analysis sampling control A defect analysis sampling control system comprising a base setting module, a lot setting module, and a work in process (WIP) prediction module. The base setting module is used for choosing and setting a corresponding sampling rule in accordance with different semic...	11/22/2005

PatentStorm

Bizarre Patents

PatentStorm News

Assignee: Grace Semiconductor Manufacturing Corporation