Assignee: GlobalFoundries, Inc.

Location: Grand Cayman, KY
No. of patents: 39

Number	Title	Issue Date
8174010	Unified test structure for stress migration tests A unified test structure which is applicable for all levels of a semiconductor device including a current path chain having a first half chain and a second half chain, wherein each half chain comprises lower metallization segments, upper metallization segments, an i...	05/08/2012
8164145	Three-dimensional transistor with double channel configuration A three-dimensional double channel transistor configuration is provided in which a second channel region may be embedded into the body region of the transistor, thereby providing a three-state behavior, which may therefore increase functionality of conventional thre...	04/24/2012
8040140	Method and apparatus for identifying broken pins in a test socket A method includes scanning a test socket after removal of a device under test to generate scan data. The scan data is compared to reference data. A presence of at least a portion of a pin in the test socket is identified based on the comparison. A test system includ...	10/18/2011
8030709	Metal gate stack and semiconductor gate stack for CMOS devices A semiconductor gate stack comprising a silicon oxide based gate dielectric and a doped semiconductor material is formed on a semiconductor substrate. A high-k material metal gate electrode comprising a high-k gate dielectric and a metal gate portion is also formed ...	10/04/2011
8030154	Method for forming a protection layer over metal semiconductor contact and structure formed thereon In one embodiment, a method of forming a semiconductor device is provided that includes providing a gate structure on a semiconductor substrate. Sidewall spacers may be formed adjacent to the gate structure. A metal semiconductor alloy may be formed on the upper sur...	10/04/2011
8028531	Mitigating heat in an integrated circuit The present invention provides for a system and method for regulating and monitoring heat dissipation of an integrated circuit by employing a heat regulating device with a thermal structure net work assembly. Each thermal structure can act as a heat conducting pathw...	10/04/2011
8019921	Intelligent memory buffer A technique reduces cost, complexity and/or power consumption of a memory system by including intelligence in a memory buffer circuit of the memory system. An apparatus includes a memory buffer circuit configured to selectively operate in one of a plurality of modes...	09/13/2011
8017411	Dynamic adaptive sampling rate for model prediction A method and an apparatus for dynamically adjusting a sampling rate relating to wafer examination. A process step is performed upon a plurality of workpieces associated with a lot. A sample rate for acquiring metrology data relating to at least one of the processed ...	09/13/2011
8010915	Grid-based fragmentation for optical proximity correction in photolithography mask applications An optical proximity correction (OPC) method for photolithography applications can be utilized to reduce the processing time, cost, and post-OPC file size associated with conventional methods. The OPC method provides a target layout pattern that represents a corresp...	08/30/2011
8009584	System and method for implementing an IRC across multiple network devices A system includes a plurality of network devices and an external memory. Each network device includes an address table. The external memory includes a group of address tables corresponding to the address tables of the network devices. The system monitors the address...	08/30/2011
7985639	Method for fabricating a semiconductor device having a semiconductive resistor structure Methods are provided for fabricating a semiconductor device. A method forms a conductive fin arrangement on a first region of a semiconductor substrate. The method continues by forming a semiconductive resistor structure on a second region of the semiconductor subst...	07/26/2011
7983362	Programmable data sampling receiver for digital data signals Receiver architectures and bias circuits for a data processor are provided. A receiver architecture includes a linear receiver having a first input node for a data (DQ) signal, a second input node for a reference voltage, and output nodes for a differential output s...	07/19/2011
7981749	MOS structures that exhibit lower contact resistance and methods for fabricating the same MOS structures that exhibit lower contact resistance and methods for fabricating such MOS structures are provided. In one method, a semiconductor substrate is provided and a gate stack is fabricated on the semiconductor substrate. An impurity-doped region within the...	07/19/2011
7977180	Methods for fabricating stressed MOS devices Methods for fabricating stressed MOS devices are provided. In one embodiment, the method comprises providing a silicon substrate having a P-well region and depositing a polycrystalline silicon gate electrode layer overlying the P-well region. P-type dopant ions are ...	07/12/2011
7977160	Semiconductor devices having stress relief layers and methods for fabricating the same Methods are provided for fabricating a semiconductor device. In accordance with an exemplary embodiment, a method comprises the steps of providing a semiconductor die having a conductive terminal, forming an insulating layer overlying the semiconductor die, and form...	07/12/2011
7974724	Product-related feedback for process control A method, apparatus, and a system for performing a product feedback for process control are provided. Metrology data relating to a first workpiece is received. An end of line parameter relating to the first workpiece is received. The end of line parameter is correla...	07/05/2011
7964970	Technique for enhancing transistor performance by transistor specific contact design By locally adapting the size and/or density of a contact structure, for instance, within individual transistors or in a more global manner, the overall performance of advanced semiconductor devices may be increased. Hence, the mutual interaction between the contact ...	06/21/2011
7888269	Triple layer anti-reflective hard mask A method includes forming a layer of silicon oxynitride (SiON), silicon rich nitride (SiRN) or silicon nitride (Si3N4) over a layer of semiconducting material. The method further includes forming a first layer of anti-reflective material over t...	02/15/2011
7885405	Multi-gigabit per second concurrent encryption in block cipher modes One embodiment is a system adapted to encrypt one or more packets of plaintext data in cipher-block chaining (CBC) mode. The system includes a plurality of digital logic components connected in series, where respective components are operative to process one or more...	02/08/2011
7881303	Command packet packing to mitigate CRC overhead In an embodiment, a node comprises a packet scheduler configured to schedule packets to be transmitted on a link and an interface circuit coupled to the packet scheduler and configured to transmit the packets on the link. The interface circuit is configured to gener...	02/01/2011
7863128	Non-volatile memory device with improved erase speed A memory device may include a substrate, a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may also include a second dielectric layer formed over the charge storage element and a...	01/04/2011
7829466	Methods for fabricating FinFET structures having different channel lengths Methods for fabricating FinFET structures having gate structures of different gate widths are provided. The methods include the formation of sidewall spacers of different thicknesses to define gate structures of the FinFET structures with different gate widths. The ...	11/09/2010
7817727	Hybrid output driver for high-speed communications interfaces A driver circuit that consumes less current than other driver circuits combines a current-mode driver circuit with a voltage-mode driver circuit to provide impedance matching and signal equalization operations. In at least one embodiment of the invention, an apparat...	10/19/2010
7782844	Method and apparatus for pattern matching on single and multiple pattern structures The present invention provides a method and apparatus for detecting and decoding data. The method comprises: receiving a set of data signals from an external data source; detecting a size of said received set of data signals; decoding said received set of data signa...	08/24/2010
7765425	Incrementally adjustable skew and duty cycle correction for clock signals within a clock distribution network A system and method for using variable delay adjusters located at various points across an integrated circuit to measure clock skew and jitter for clock signals of the integrated circuit. A delay controller of the integrated circuit may measure and compensate for cl...	07/27/2010
7739498	Method and apparatus for multi-table accessing of input/output devices using target security A method and an apparatus for performing an I/O device access using targeted security. A software object is executed. A security level for the software object is established. A multi-table input/output (I/O) space access is performed using at least one of the securi...	06/15/2010
7738986	Method and apparatus for compensating metrology data for site bias prior to filtering A method includes acquiring metrology data associated with a process. Bias information associated with the process is determined. The metrology data is adjusted based on the bias information to generate bias-adjusted metrology data. The bias-adjusted metrology data ...	06/15/2010
7700377	Method for reducing etch-induced process uniformities by omitting deposition of an endpoint detection layer during patterning of stressed overlayers in a semiconductor device During the patterning of respective contact etch stop layers having a different type of intrinsic stress, the deposition of an etch indicator layer between the first and the second contact etch stop layer may be omitted in order to avoid any undue effects of this la...	04/20/2010
7695986	Method and apparatus for modifying process selectivities based on process state information The present invention provides a method and apparatus for modifying process selectivities based on process state information. The method includes accessing process state information associated with at least one material removal process, determining at least one sele...	04/13/2010
7672749	Method and apparatus for hierarchical process control The present invention provides a method and apparatus for hierarchical process control. The method includes accessing at least one first metric indicative of processing performed on a wafer by a plurality of tool groups. The method also includes providing at least o...	03/02/2010
7670938	Methods of forming contact openings The present invention is directed to methods of forming contact openings. In one illustrative embodiment, the method includes forming a feature above a semiconducting substrate, forming a layer stack comprised of a plurality of layers of material above the feature, ...	03/02/2010
7668615	Method and apparatus for randomizing dispatch order for single wafer processing A method for dispatching wafers for processing in a tool includes identifying a queue of wafers available to be processed in the tool. One of the wafers is randomly selected based at least in part on a length of time each wafer has been in the queue. The selected wa...	02/23/2010
7667842	Structure and method for simultaneously determining an overlay accuracy and pattern placement error The present invention provides a technique for obtaining overlay error and PPE error information from a single measurement structure. This is accomplished by forming periodic sub-structures in at least two different device layers in a single measurement structure, w...	02/23/2010
7659213	Transistor having an embedded tensile strain layer with reduced offset to the gate electrode and a method for forming the same By incorporating carbon by means of ion implantation and a subsequent flash-based or laser-based anneal process, strained silicon/carbon material with tensile strain may be positioned in close proximity to the channel region, thereby enhancing the strain-inducing me...	02/09/2010
7659170	Method of increasing transistor drive current by recessing an isolation trench By recessing the isolation structure of a transistor prior to silicidation, the series resistance may be reduced due to the increased amount of metal silicide formed in the vicinity of the isolation structure. By recessing the isolation structure prior to the format...	02/09/2010
7657339	Product-related feedback for process control A method, apparatus, and a system for performing a product feedback for process control are provided. Metrology data relating to a first workpiece is received. An end of line parameter relating to the first workpiece is received. The end of line parameter is correla...	02/02/2010
7646470	Immersion lithographic process using a variable scan speed A lithography system and a lithography method is provided for increasing reliability and efficiency of immersion lithography. By varying a scan speed between a wafer and an optical component depending on at least one process parameter during exposure of the wafer, l...	01/12/2010
7638428	Semiconductor structure and method of forming the same A method of forming a semiconductor structure comprises providing a semiconductor substrate comprising a layer of a dielectric material. A recess is provided in the layer of dielectric material. The recess is filled with a material comprising silver. ...	12/29/2009
7638424	Technique for non-destructive metal delamination monitoring in semiconductor devices By providing large area metal plates in combination with respective peripheral areas of increased adhesion characteristics, delamination events may be effectively monitored substantially without negatively affecting the overall performance of the semiconductor devic...	12/29/2009

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Assignee: GlobalFoundries, Inc.