Assignee: Freescale Semiconductor, Inc.

Location: Austin, TX
No. of patents: 2743

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Number	Title	Issue Date
8185798	Techniques for reducing joint detection complexity in a channel-coded multiple-input multiple-output communication system A technique for joint detection of channel-coded signals in a multiple-input multiple-output system includes detecting, when a decoded signal associated with a first symbol stream passes a cyclic redundancy check, channel-coded signals in the first symbol stream and...	05/22/2012
8185773	Processor system employing a signal acquisition managing device and signal acquisition managing device A processor system having a processor core configured to control an external apparatus in accordance with a control algorithm; a signal acquisition managing device configured to receive state signals provided by the apparatus, perform corresponding actions, and gene...	05/22/2012
8184812	Secure computing device with monotonic counter and method therefor A secure computing device (14) includes a secure processing section (30) having a tamper detection circuit (58) and a monotonic counter (68). The tamper detection circuit (58) detects an event which suggests that the trust associat...	05/22/2012
8184750	Techniques for increasing decoding reliability in an adaptive minimum mean squared error with successive interference cancellation (MMSE/SIC) decoder A technique for increasing decoding reliability in an adaptive minimum mean squared error with successive interference cancellation (MMSE/SIC) decoder in a channel-coded multiple-input multiple-output (MIMO) communication system. A code block selector evaluates reli...	05/22/2012
8184027	Semiconductor device and differential amplifier circuit therefor A differential amplifier circuit comprising a differential amplifier capacitor and a mismatch error cancellation circuitry, a first pair of capacitors, a second pair of capacitors consisting of switching network. The switching network is arranged to operate in a fir...	05/22/2012
8183639	Dual port static random access memory cell layout A dual port static random access memory cell has pull-down transistors, pull-up transistors, and pass transistors. A first active region has a first pull-down transistor coupled to a true data node, a second pull-down transistor coupled to a complementary data node;...	05/22/2012
8183160	Method for manufacturing a semiconductor device and semiconductor device obtainable with such a method A method for manufacturing a semiconductor device includes providing a patterned hard-mask layer. The hard-mask layer is provided on an exposed surface of one or more layers to be patterned of a semiconductor intermediate product. The hard-mask layer covers the expo...	05/22/2012
8181098	Error correcting Viterbi decoder Methods and corresponding systems in a Viterbi decoder include computing a maximum likelihood (ML) path in a Viterbi trellis in response to executing a first Viterbi algorithm. Thereafter, one or more merge points are selected on the ML path in a second Viterbi algo...	05/15/2012
8181051	Electronic apparatus and method of conserving energy An electronic apparatus and a method of conserving energy comprises providing an energy-conservation module to control use of one or more energy-saving mechanism by a hardware element. The energy-conservation module comprises a performance estimation module that est...	05/15/2012
8181049	Method for controlling a frequency of a clock signal to control power consumption and a device having power consumption capabilities A method for controlling power consumption of a processor, the method includes: receiving an indicator that indicates that the processor is expected to change its activity; determining, in response to the indicator and to a current power consumption of the processor...	05/15/2012
8180969	Cache using pseudo least recently used (PLRU) cache replacement with locking A cache stores information in each of a plurality of cache lines. Addressing circuitry receives memory addresses for comparison with multiple ways of stored addresses to determine a hit condition representing a match of a stored address and a received address. A pse...	05/15/2012
8180007	Method for clock and data recovery An input bit stream including a clock signal and data bits is oversampled to obtain one or more sets of data samples. One or more sets of non-transitioning phases corresponding to data samples that do not switch between zero and one are then identified. Center phase...	05/15/2012
8179187	Substrate noise passive cancellation method for buck converter A method for passive cancellation of substrate noise for a buck converter uses an on-chip capacitor to reduce the substrate noise. The capacitor achieves a close-magnitude noise with opposite phase for better noise cancellation effect in the substrate. The capacitor...	05/15/2012
8179108	Regulator having phase compensation circuit A regulator circuit includes an output transistor that generates an output current in accordance with a control voltage that is applied to a control terminal of the output transistor. A differential amplifier provides feedback control of the control voltage in accor...	05/15/2012
8179051	Serial configuration for dynamic power control in LED displays A power management technique in a light emitting diode (LED) system is disclosed. The LED system includes a plurality of LED driver connected in series, each LED driver configured to regulate the current flowing through a corresponding subset of a plurality of LED s...	05/15/2012
8178950	Multilayered through a via A method for forming a through substrate via (TSV) comprises forming an opening within a substrate. An adhesion layer of titanium is formed within the via opening, a nucleation layer of titanium nitride is formed over the adhesion layer, and a tungsten layer is depo...	05/15/2012
8178942	Electrically alterable circuit for use in an integrated circuit device An electrically alterable circuit (EAC), suitable for use in an integrated circuit, includes a first interconnect, a link element, and a second interconnect. A first set of interconnect vias provides an electrically conductive connection between the first interconne...	05/15/2012
8178406	Split gate device and method for forming A method of making a semiconductor device on a semiconductor layer includes forming a select gate, a recess, a charge storage layer, and a control gate. The select gate is formed have a first sidewall over the semiconductor layer. The recess is formed in the semicon...	05/15/2012
8178401	Method for fabricating dual-metal gate device A method of fabricating a MOS transistor that comprises a dual-metal gate that is formed from heterotypical metals. A gate dielectric (34), such as HfO2, is deposited on a semiconductor substrate. A sacrificial layer (35), is next deposited ...	05/15/2012
8177426	Sub-threshold CMOS temperature detector A CMOS temperature detection circuit includes a start-up circuit for generating a start-up voltage (VN), and a proportional to absolute temperature (PTAT) current generator coupled to the start-up circuit for generating a PTAT current. The start-up voltage turns on ...	05/15/2012
8176340	Method and system for initializing an interface between two circuits of a communication device while a processor of the first circuit is inactive and waking up the processor thereafter A method and system for managing communications between sub-systems of a communication device. The sub-systems include a Radio Frequency Integrated Circuit (RFIC) and a Baseband Integrated Circuit (BBIC). The BBIC includes a processing engine, a state machine module...	05/08/2012
8176227	Method and system for high-speed detection handshake in universal serial bus based data communication system A USB system includes a USB hub, a USB device, and a USB bus interconnecting the USB hub and the USB device. The USB hub asserts a reset signaling on the USB bus to initiate a high-speed detection handshake. The USB hub and the USB device activate corresponding dual...	05/08/2012
8175737	Method and apparatus for designing and integrated circuit Method and apparatus for designing an integrated circuit by adding a plurality of control points to an integrated circuit wafer design. Each control point has at least one attribute. Then, an integrated circuit wafer is manufactured using the integrated circuit wafe...	05/08/2012
8175560	Method and system for tuning an antenna Method and system for tuning a tunable antenna uses a comparison between a signal response at two different tuning frequencies to determine how or if the tuning needs to be further adjusted. With the approach, the method and system arrive at a frequency shift that i...	05/08/2012
8175548	Method and device for transmitting a sequence of transmission bursts Methods and device for transmitting a sequence of transmission bursts in a wireless device. The method includes transmitting a sequence of transmission bursts according to a transmission schedule. The method is characterized by: receiving, at a radio frequency integ...	05/08/2012
8175276	Encryption apparatus with diverse key retention schemes An encryption apparatus (14) includes a secure processing system (12) in the form of an integrated circuit. The secure processing system (12) includes an on-chip secure memory system (30). The secure memory system (30) includes a n...	05/08/2012
8175213	System and method for setting counter threshold value A system and method for configuring threshold values for fixed time delay counters of a System on a Chip (SoC) uses a reference clock signal and one or more frequency sub-range control signals corresponding to a frequency sub-range of the reference clock signal. A f...	05/08/2012
8174279	Socket connector for connection lead of semiconductor device under test with tester A socket connector for electrically connecting a lead of a semiconductor device under test (DUT) with a tester includes a container having a chamber, a conductive end or plug that seals the chamber at one end, and a conductive membrane that seals the chamber at anot...	05/08/2012
8174251	Series regulator with over current protection circuit A series regulator with an over current protection circuit regulates output current by controlling an output transistor. A current sense transistor output depends on the conductivity of the output transistor. A current limiting transistor controls the conductivity o...	05/08/2012
8173505	Method of making a split gate memory cell A method includes forming a first layer of gate material over a semiconductor substrate; forming a hard mask layer over the first layer; forming an opening; forming a charge storage layer over the hard mask layer and within the opening; forming a second layer of gat...	05/08/2012
8171384	Device having turbo decoding capabilities and a method for turbo decoding A device and a method for turbo decoding, the method includes performing multiple iterations of a turbo decoding process until a turbo decoding process is completed; wherein the performing comprises repeating the stages of: (i) initializing at least one state metric...	05/01/2012
8171336	Method for protecting a secured real time clock module and a device having protection capabilities A method for protecting a secured real time clock module, the method includes: locking multiple input ports of the secured real time clock module if the multiple input ports of the secured real time clock module are idle during at least a first duration; unlocking t...	05/01/2012
8171187	System and method for arbitrating between memory access requests A system having memory access capabilities, the system includes: (i) a dynamic voltage and frequency scaling (DVFS) controller, adapted to determine a level of a voltage supply supplied to a first memory access requester and a frequency of a clock signal provided to...	05/01/2012
8170509	Incident and reflected signal phase difference detection Embodiments include methods and apparatus for detecting a phase angle between an incident signal and a reflected signal. The apparatus comprises a plurality of phase shifters and additional circuitry. The plurality of phase shifters is adapted to apply first phase s...	05/01/2012
8170166	Methods and systems for combining timing signals for transmission over a serial interface Apparatus, systems, and methods are provided for transmitting messages over a serial interface. A method comprises receiving a first signal at a first time and receiving a second signal at a second time, the second time being after the first time. If a difference be...	05/01/2012
8169978	Techniques for frequency-domain joint detection in wireless communication systems A technique of operating a wireless communication device includes receiving, at a first wireless communication device, respective signals transmitted from multiple second wireless communication devices. Respective channel matrix blocks for each block of the received...	05/01/2012
8169257	System and method for communicating between multiple voltage tiers A system includes first, second, and third circuits and first and second capacitors. The first capacitor has a first power supply terminal coupled to positive power supply terminal, a second power supply terminal, and an input/output. The second capacitor has a firs...	05/01/2012
8169245	Duty transition control in pulse width modulation signaling A pulse width modulation (PWM) signal generator generates a PWM signal with an adjustable PWM duty based on a programmable or otherwise adjustable value. In response to a change or update to this value, the PWM signal generator initiates a duty transition process th...	05/01/2012
8168468	Method of making a semiconductor device including a bridgeable material A method for making a semiconductor device (10) includes providing an interconnect layer (14) over an underlying layer (12), forming a first insulating layer (16) over the interconnect layer, and forming an opening (18) through the...	05/01/2012
8168464	Microelectronic assembly with an embedded waveguide adapter and method for forming the same A microelectronic assembly and a method for forming a microelectronic assembly are provided. A semiconductor substrate (22) is provided. The semiconductor substrate (22) has first and second opposing sides (24, 26) and first and second portions ...	05/01/2012

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Assignee: Freescale Semiconductor, Inc.