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...When G.G. Hubbard learned of his future son-in-law's invention, he called it "only a toy." His daughter was engaged to a young man named Alexander Graham Bell.
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| Number | Title | Issue Date |
| 7945767 | Recovery apparatus for solving branch mis-prediction and method and central processing unit thereof A recovery apparatus for solving a branch mis-prediction, and a method and a central processing unit (CPU) thereof are provided. The recovery apparatus includes an instruction buffer, at least one circular instruction buffer, and a decoding and pairing circuit. The ... | 05/17/2011 |
| 7795926 | Phase detector for half-rate bang-bang CDR circuit A phase detector, including a sampling device, a comparing device, and an output device, is provided. The sampling device samples a data signal according to a plurality of clock signals, so as to provide a plurality of corresponding sampling values. The clock signal... | 09/14/2010 |
| 7738451 | Method and device for flexible buffering in networking system A method and device for flexible, dynamic and optimal buffering in a networking system are provided. Sizes of incoming packets are recognized and the packets are buffered into buffers of appropriate sizes. Usage times of buffers are counted, and during an idle state... | 06/15/2010 |
| 7730289 | Method for preloading data in a CPU pipeline A method for preloading data in a CPU pipeline is provided, which includes the following steps. When a hint instruction is executed, allocate and initiate an entry in a preload table. When a load instruction is fetched, load a piece of data from a memory into the en... | 06/01/2010 |
| 7716542 | Programmable memory built-in self-test circuit and clock switching circuit thereof A programmable memory built-in self-test circuit and a clock switching circuit thereof are provided. The memory built-in self-test circuit is able to provide more self-test functions preset by a user, simplify the redundant circuit in the prior art and reduce chip a... | 05/11/2010 |
| 7707521 | Layout architecture having high-performance and high-density design A layout architecture having high-performance and high-density design used in a standard cell integrated circuit is provided. The layout architecture includes a substrate, a first conductor, a second conductor, a third conductor, a fourth conductor, a first device r... | 04/27/2010 |
| 7707336 | Universal serial bus (USB) system with single port and host controller thereof A universal serial bus (USB) with single port and a host controller thereof are provided. The USB comprises a USB port, a speed detection circuitry, a start of frame (SOF) generator, and a host controller. The USB port is electrically coupled to an external circuitr... | 04/27/2010 |
| 7706115 | Over-voltage indicator and related circuit and method Over-voltage indicator and related circuit and method. The over-voltage indicator can work with an I/O circuit of a chip for detecting over-voltage in an I/O pad and providing an indication signal accordingly. When over-voltage does not happen, the over-voltage indi... | 04/27/2010 |
| 7701041 | Chip-packaging with bonding options having a plurality of package substrates Chip-packaging with bonding options having a plurality of package substrates. The chip-packaging includes first and second package substrates, a chip, and a lead. The chip having a plurality of bonding pads is mounted on the first package substrate. One of these bon... | 04/20/2010 |
| 7684402 | Method and network device for fast look-up in a connection-oriented communication A method for fast look-up in a connection-oriented communication includes generating a connection associated information according to peer information of a first peer and a second peer, storing the connection associated information into the first peer and the second... | 03/23/2010 |
| 7679352 | Bandgap reference circuits A bandgap reference circuit comprises: a current generator for generating an output current, the current generator comprising a first reference unit and a plurality of second reference units arranged in parallel, where the current generator is capable of determining... | 03/16/2010 |
| 7676109 | Deblocking method according to computing mode determined from a first value and a second value, the second value determined according to precisely eight pixels A deblocking method, for removing blocking artifacts comprises selecting a plurality of first pixels according to a bandwidth of a memory device, wherein the first pixels are uniformly distributed at two sides of a block boundary; calculating a first value according... | 03/09/2010 |
| 7675308 | Test circuit and test method for power switch For on-chip testing an on-chip power switch coupled to a core logic and to a decoupling capacitance, after the power switch enters a test mode, the decoupling capacitance is pre-charged or discharged; the power switch is turned ON or OFF according to test patterns; ... | 03/09/2010 |
| 7664941 | Branch prediction methods and devices capable of predicting first taken branch instruction within plurality of fetched instructions A branch prediction method, capable of predicting a first taken branch instruction within a plurality of fetched instructions, includes: determining whether one of the fetched instructions is the first taken branch instruction to be predicted according to hint instr... | 02/16/2010 |
| 7656214 | Spread-spectrum clock generator A spread-spectrum clock generator is provided, which includes a modulation module and a voltage-controlled delay line (VCDL). The modulation module provides a control voltage. The VCDL is coupled to the modulation module and is configured for modulating the frequenc... | 02/02/2010 |
| 7615412 | System in package (SIP) integrated circuit and packaging method thereof The present invention discloses a system in package (SIP) integrated circuit and a packaging method thereof. The SIP integrated circuit includes one or more first block dices produced by a first process and one or more second block dices produced by a second process... | 11/10/2009 |
| 7603598 | Semiconductor device for testing semiconductor process and method thereof A semiconductor device for testing a semiconductor process applied to manufacturing the semiconductor device is disclosed. The semiconductor device includes at least a testing group. The testing group includes a first testing block and a second testing block. The fi... | 10/13/2009 |
| 7596772 | Methodology and system for setup/hold time characterization of analog IP A fast methodology and system to characterize setup/hold time for analog IPs are provided. Partial circuits of clock and data paths are simulated instead of the simulation of entire IPs. The partial circuits include all those paths of clock pin and data input pins b... | 09/29/2009 |
| 7596728 | Built-in self repair circuit for a multi-port memory and method thereof A built-in self repair (BISR) circuit for a multi-port memory and a method thereof are provided. The circuit includes a test-and-analysis module (TAM) and a defect locating module (DLM) coupled to the TAM. The TAM tests a repairable multi-port memory to generate a f... | 09/29/2009 |
| 7593745 | Method for operating wireless local area network cards in a power-saving mode A method for a wireless access point for operating WLAN cards in a power-saving mode in a wireless communication system. The method includes: (a) storing data to be transmitted to the WLAN cards in the wireless access point of the wireless communication system; (b) ... | 09/22/2009 |
| 7583752 | Transmitter for outputting differential signals of different voltage levels A differential signal transmitter including a driver circuit that generates a differential signal in response to data input. The amplitude of the voltage swings in the differential circuit is controlled by an electrical bias. Two data inputs, one being the original ... | 09/01/2009 |
| 7567640 | Phase offset tracking method for tracking a phase offset and device thereof The invention relates to a phase offset tracking module and method for tracking a phase offset, and in particular, to a phase offset tracking module and method for tracking a phase offset in a receiver. A phase offset tracking method comprises: utilizing a first and... | 07/28/2009 |
| 7567533 | Packet detection system, packet detection device, and method for receiving packets A packet detector for a multi-band orthogonal frequency division multiplexing system includes a plurality of packet detection units each corresponding to a time frequency code for detecting packets according to a spreading sequence of the time frequency code, a comp... | 07/28/2009 |
| 7564285 | Controllable delay line and regulation compensation circuit thereof A controllable delay line includes an anti-jitter unit, a dependent current source, a first current mirror, a second current mirror, a regulation capacitor, a compensation capacitor and an output buffer unit. The anti-jitter unit receives a first bias voltage and pr... | 07/21/2009 |
| 7512856 | Register circuit, scanning register circuit utilizing register circuits and scanning method thereof The present invention discloses a register circuit. The register circuit includes a latch circuit for latching an input data to generate an output data; an input signal selecting circuit, coupled to a non-test data and a test data respectively, for selectively outpu... | 03/31/2009 |
| 7495479 | Sample and hold circuit and related data signal detecting method utilizing sample and hold circuit Disclosed is a sample and hold circuit for detecting a parameter of a data signal, which includes: a first switching module, wherein the sample and hold circuit samples the data signal according to the turning on or off of the first switching module; at least one ca... | 02/24/2009 |
| 7493600 | Method for verifying branch prediction mechanism and accessible recording medium for storing program thereof A method for verifying a branch prediction mechanism and an accessible recording medium for storing a verification program are provided. The method is used for verifying the branch prediction mechanism, such as a branch target buffer (BTB), in a processor. The metho... | 02/17/2009 |
| 7479698 | Bonding pad structure disposed in semiconductor device and related method The present invention discloses a bonding pad structure disposed in a semiconductor device and a method for forming the bonding pad structure. The semiconductor device includes a substrate. The bonding pad structure includes a connection structure and an induction s... | 01/20/2009 |
| 7471158 | Automatic switching phase-locked loop An automatic switching phase-locked loop (PLL) is disclosed, including a phase detector, a charge pump generating a pump current, a band selector receiving a control voltage to produce a band selection signal and a voltage setting signal based the control voltage, a... | 12/30/2008 |
| 7471126 | Phase locked loop utilizing frequency folding A phase locked loop (PLL), including a phase-frequency detector receiving two clock signals and outputting a phase detection signal corresponding to the phase difference between the two clock signals is provided. A controller receives the phase detection signal and ... | 12/30/2008 |
| 7464357 | Integrated circuit capable of locating failure process layers An integrated circuit for locating failure process layers. The circuit has a substrate with a scan chain disposed therein, having scan cells connected to form a series chain. Each connection is formed according to a layout constraint of a minimum dimension provided ... | 12/09/2008 |
| 7463102 | Clock synthesizer with clock divider outside feedback loop and method thereof A de-skew multiplier clock synthesizer with a clock divider outside the feedback loop of a PLL is provided. The clock synthesizer includes a phase locked loop (PLL), a clock divider, and a phase comparator. The PLL receives a reference clock and generates a PLL outp... | 12/09/2008 |
| 7451356 | Apparatus for configuring network media connections Apparatus for configuring network media connections. A medium-dependent interface crossover includes a first input terminal set comprising a first input pair and a first enabling pair, a second input terminal set comprising a second input pair and a second enabling ... | 11/11/2008 |
| 7429886 | Poly fuse trimming circuit A poly fuse trimming circuit. The poly fuse trimming circuit comprises a poly fuse and a silicon controlled rectifier (SCR) device. The poly fuse is coupled between a first fixed potential and an output node. The SCR device is controlled by a trimming signal and has... | 09/30/2008 |
| 7415161 | Method and related processing circuits for reducing memory accessing while performing de/compressing of multimedia files Method and apparatus for reducing memory access while de/compressing multimedia files, videos, or image files. An image is divided into blocks, and a frequency data matrix corresponding to a frequency transformed and quantized block is stored in a memory for later d... | 08/19/2008 |
| 7412019 | Spread spectrum clock generator A spread spectrum clock generator comprising a phase-locked loop circuit and a modulation circuit. The phase-locked loop circuit receives a reference signal at a reference frequency and outputs an output signal at an output frequency periodically varying in a range ... | 08/12/2008 |
| 7411380 | Non-linearity compensation circuit and bandgap reference circuit using the same A non-linearity compensation circuit and a bandgap reference circuit using the same for compensating non-linear effects of a reference voltage are provided. In the non-linearity compensation circuit, the reference voltage is transformed into a temperature independen... | 08/12/2008 |
| 7394272 | Built-in self test for system in package A SIP (system in package) with a chip and a memory mode, capable of performing integration test on the memory module even if the memory module does not include any scan chain is provided. The chip has a built-in self-test (BIST) circuit, which generates test pattern... | 07/01/2008 |
| 7394241 | Method and apparatus for testing power switches using a logic gate tree A method for testing power switches using a logic gate tree, the method includes providing a logic gate tree electrically connected to a plurality of power switches, each output node of the plurality of power switches being electrically connected to a corresponding ... | 07/01/2008 |
| 7391837 | Newton's method-based timing recovery circuit A Newton's method-based timing recovery circuit is provided for to solving a polynomial accurately. The timing recovery circuit can generate an interpolation signal, whose timing errors are confined within a predetermined timing error range, which corresponds to a d... | 06/24/2008 |
