Did You Know...
...that the x-ray was discovered purely by accident? When German physicist Wilhelm Konrad von Roentgen was experimenting with cathode rays in 1895, he put an activated Crookes tube in a book and went out to lunch. When he returned, he discovered that a key that had also been placed in the book showed up as an image on the developed film!
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| Number | Title | Issue Date |
| 8183892 | Monolithic low impedance dual gate current sense MOSFET A power switch includes a first power transistor having a first source electrode, a first gate electrode, and a first drain electrode, and a second power transistor having a second source electrode, a second gate electrode, and a second drain electrode. The power sw... | 05/22/2012 |
| 8183088 | Semiconductor die package and method for making the same Semiconductor die packages are disclosed. An exemplary semiconductor die package includes a premolded substrate. The premolded substrate can have a semiconductor die attached to it, and an encapsulating material may be disposed over the semiconductor die. ... | 05/22/2012 |
| 8179151 | Method and system that determines the value of a resistor in linear and non-linear resistor sets The present invention employs identically sized mirror transistors arrange in groups that may be preferentially addressed and activated to determine the value of a resistor. Known current are directed through the resistor, and the voltage developed is measured by co... | 05/15/2012 |
| 8174067 | Trench-based power semiconductor devices with increased breakdown voltage characteristics Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed. ... | 05/08/2012 |
| 8168473 | Molded ultra thin semiconductor die packages, systems using the same, and methods of making the same Disclosed are molded ultra-thin semiconductor die packages, systems that incorporate such packages, and methods of making such packages. An exemplary package comprises a leadframe having an aperture formed between the leadframe's first and second surfaces, and a plu... | 05/01/2012 |
| 8148749 | Trench-shielded semiconductor device Various structures and methods for improving the performance of trench-shielded power semiconductor devices and the like are described. An exemplary device comprises a semiconductor region having a surface, a first area of the semiconductor region, a well region of ... | 04/03/2012 |
| 8148233 | Semiconductor power device having a top-side drain using a sinker trench A semiconductor power device includes a plurality of groups of stripe-shaped gate trenches extending in a silicon region over a substrate, and a plurality of stripe-shaped sinker trenches each extending between two adjacent groups of the plurality of groups of strip... | 04/03/2012 |
| 8143993 | Method and circuit for recycling trimmed devices A trimmable component network of switched parallel paths is described, each path contains a component, typically a resistor, with a portion of the component bypassed by fuses. The bypassed portion represents the same percentage of the component's value for each of t... | 03/27/2012 |
| 8143845 | Cable voltage drop compensation for battery chargers A battery charger may be configured to charge a battery by way of a charging cable. A DC gain of a voltage control loop of the battery charger may be limited to a predetermined value to compensate for voltage drop on the charging cable. For example, a DC gain of an ... | 03/27/2012 |
| 8143679 | Termination structure for power devices A semiconductor power device includes an active region configured to conduct current when the semiconductor device is biased in a conducting state, and a termination region along a periphery of the active region. The termination region includes a first silicon regio... | 03/27/2012 |
| 8143125 | Structure and method for forming a salicide on the gate electrode of a trench-gate FET A method for forming a trench-gate FET includes the following steps. A plurality of trenches is formed extending into a semiconductor region. A gate dielectric is formed extending along opposing sidewalls of each trench and over mesa surfaces of the semiconductor re... | 03/27/2012 |
| 8143124 | Methods of making power semiconductor devices with thick bottom oxide layer A method of manufacturing a semiconductor device having a charge control trench and an active control trench with a thick oxide bottom includes forming a drift region, a well region extending above the drift region, an active trench extending through the well region... | 03/27/2012 |
| 8143123 | Methods of forming inter-poly dielectric (IPD) layers in power semiconductor devices A method for forming power semiconductor devices having an inter-electrode dielectric (IPD) layer inside a trench includes providing a semiconductor substrate with a trench, lining the sidewalls and bottom of the trench with a first layer of dielectric material, fil... | 03/27/2012 |
| 8138739 | Circuits and methods for improving transient response of hysteretic DC-DC converters A hysteretic DC-DC converter includes an observer circuit configured to generate an observer control signal for injection into the control loop of the converter. The observer circuit may be configured to differentiate the output voltage of the converter to generate ... | 03/20/2012 |
| 8138585 | Four mosfet full bridge module A molded, leadless packaged semiconductor multichip module includes 100 has four mosfets 10, 12, 14, 16 for a full bridge circuit. The mosfets may include two N-channel and two P-channel devices or four mosfets of the same type, but four N-channel are ... | 03/20/2012 |
| 8138081 | Aluminum bump bonding for fine aluminum wire The invention includes a packaged semiconductor device in which the bond wires are bonded to the leads with an aluminum bump bond. The semiconductor device is mounted on a leadframe having leads with a nickel plating. To form the bump bond between a fine aluminum wi... | 03/20/2012 |
| 8129959 | Start-up circuitry and method for power converter In one embodiment, circuitry is provided for startup of a power converter. The circuitry includes a bias capacitor operable to be charged for providing energy to a controller of the power converter. A divider circuit is coupled to a voltage source. Current flows thr... | 03/06/2012 |
| 8129245 | Methods of manufacturing power semiconductor devices with shield and gate contacts Methods of manufacturing power semiconductor devices include forming an epitaxial and dielectric layer, patterning and etching the dielectric layer, forming a first oxide layer, forming a first conductive layer on top of the first oxide layer, etching the first cond... | 03/06/2012 |
| 8129241 | Method for forming a shielded gate trench FET A method for forming a shielded gate field effect transistor (FET) includes forming a plurality of trenches in a semiconductor region and forming a shield electrode in a bottom portion of each trench. The method also includes forming a dielectric layer comprising a ... | 03/06/2012 |
| 8125029 | Lateral power diode with self-biasing electrode A semiconductor diode includes a drift region of a first conductivity type and an anode region of a second conductivity type in the drift region such that the anode region and the drift region form a pn junction therebetween. A first highly doped silicon region of t... | 02/28/2012 |
| 8124981 | Rugged semiconductor device architecture A wide bandgap silicon carbide device has an avalanche control structure formed in an epitaxial layer of a first conductivity type above a substrate that is connected to a first electrode of the device. A first region of a second conductivity type is in the upper su... | 02/28/2012 |
| 8120169 | Thermally enhanced molded leadless package A molded leadless package (MLP) semiconductor device includes a heat spreader with a single connecting projection extending from an edge of a cap of the heat spreader to a leadframe. The heat spreader can include additional projections on its edges that act as heat ... | 02/21/2012 |
| 8119457 | Flip chip MLP with folded heat sink A semiconductor package assembly including a molded leadless package (MLP) having an exposed top emitter pad and an exposed bottom source pad. A folded heat sink is attached to the exposed top emitter pad of the MLP by a soft solder attach process. The folded heat s... | 02/21/2012 |
| 8110492 | Method for connecting a die attach pad to a lead frame and product thereof Disclosed in this specification is a semiconductor package with a die attach pad and a lead frame which are electrically and mechanically connected to one another through a conductive wire ribbon. Such a configuration reduces the package footprint and also permits d... | 02/07/2012 |
| 8110474 | Method of making micromodules including integrated thin film inductors Micromodules and methods of making them are disclosed. An exemplary micromodule includes a substrate having a thin film inductor, and a bumped die mounted on the substrate and over the thin film inductor. ... | 02/07/2012 |
| 8110447 | Method of making and designing lead frames for semiconductor packages A lead frame with patterned conductive runs on the top surface to accept a wire bonded or flip-chip or COL configuration is disclosed. The top pattern is completed and the bottom is etched away creating cavities. The cavities are filled with a pre-mold material that... | 02/07/2012 |
| 8107575 | Method and circuit for changing modes without dedicated control pin A system and process for eliminating a control wire between logic systems that communicate with each other. In one embodiment, a system sends to a receiver a frequency that indicates a first mode. In the first mode a first data type may be sent. When the frequency i... | 01/31/2012 |
| 8106501 | Semiconductor die package including low stress configuration A semiconductor die package. The semiconductor die package comprises a semiconductor die and a molded clip structure comprising a clip structure and a first molding material covering at least a portion of the clip structure. The first molding material exposes an out... | 01/31/2012 |
| 8106406 | Die package including substrate with molded device A package is disclosed. The package includes a premolded substrate having a leadframe structure, a first device attached to the leadframe structure, and a molding material covering at least part of the leadframe structure and the first device. It also includes a sec... | 01/31/2012 |
| 8102029 | Wafer level buck converter A buck converter module includes a high side (HS) die having source, drain, and gate bonding pads on a front side of the HS die, a low side (LS) die having a first section thereof with a plurality of through silicon vias (TSVs) extending from a back side to a front ... | 01/24/2012 |
| 8101996 | Three-dimensional semiconductor device structures and methods A three-dimensional semiconductor device structure includes a first semiconductor device and a second semiconductor device bonded together using a patterned conductive layer according to an embodiment of the invention. The first semiconductor device includes a first... | 01/24/2012 |
| 8101484 | Method of forming a FET having ultra-low on-resistance and low gate charge In accordance with an exemplary embodiment of the invention, a substrate of a first conductivity type silicon is provided. A substrate cap region of the first conductivity type silicon is formed such that a junction is formed between the substrate cap region and the... | 01/24/2012 |
| 8098505 | Phase management for interleaved power factor correction An interleaved power factor correction (PFC) circuit includes phase management to control shedding and adding of channels. The channels may be voltage (e.g., boost) converters connected in parallel. The interleaved PFC circuit can have a first channel and a second c... | 01/17/2012 |
| 8097510 | Method of forming lateral trench gate FET with direct source-drain current path A method of forming a field effect transistor (FET) includes: forming a drift region comprising a stack of alternating conductivity type silicon layers; forming a drain region of a first conductivity type extending into the stack of alternating conductivity type sil... | 01/17/2012 |
| 8088645 | 3D smart power module A 3D smart power module for power control, such as a three phase power control module, includes a two sided printed circuit (PC) board with power semiconductor devices attached to one side and control semiconductor devices attached to the other side. The power semic... | 01/03/2012 |
| 8085559 | Current mode control for resonant converter circuits A current mode resonant converter integrates current information from a first drive transistor to generate an integration signal. The integration signal is added to a sawtooth signal to generate a quasi-sawtooth signal. The quasi-sawtooth signal is compared to an er... | 12/27/2011 |
| 8085516 | Ground fault circuit interrupter with self test A ground fault circuit interrupter (GFCI) includes a GFCI controller configured to detect for ground faults and to periodically perform a self test. The self test may be performed during a positive half cycle of an AC line voltage coupled to a load by the GFCI. The ... | 12/27/2011 |
| 8084870 | Semiconductor devices and electrical parts manufacturing using metal coated wires The device of this invention includes a semiconductor die attached to a bare copper lead frame and electrically coupled to a lead by a metal wire coated with a metallic material. The device would function similarly to devices where the lead frames were coated with o... | 12/27/2011 |
| 8084327 | Method for forming trench gate field effect transistor with recessed mesas using spacers A method for forming a field effect transistor with an active area and a termination region surrounding the active area includes forming a well region in a first silicon region, where the well region and the first silicon region are of opposite conductivity type. Ga... | 12/27/2011 |
| 8080848 | High voltage semiconductor device with lateral series capacitive structure According to the present invention, semiconductor device breakdown voltage can be increased by embedding field shaping regions within a drift region of the semiconductor device. A controllable current path extends between two device terminals on the top surface of a... | 12/20/2011 |
