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| Number | Title | Issue Date |
| 4972251 | Multilayer glass passivation structure and method for forming the same A thick glass passivation layer comprises an alternating sequence of structurally dissimilar but chemically compatible layers of material over the surface of a substrate, so as to provide sufficient elasticity to compensate for thermal expansion differenc... | 11/20/1990 |
| 4920071 | High temperature interconnect system for an integrated circuit A semiconductor integrated circuit device is provided with an electrical interconnect system which is stable at high temperatures. The interconnect system employs refractory metal compounds which are electrically conductive, which form stable couples with... | 04/24/1990 |
| 4912344 | TTL output stage having auxiliary drive to pull-down transistor A novel output stage is provided for producing a TTL output signal in response to the differential output signals from an ECL switch. The output stage includes a translator portion to shift the levels of the complementary signals produced by the ECL switc... | 03/27/1990 |
| 4888300 | Submerged wall isolation of silicon islands To completely isolate an island of silicon, a trench is cut into an epitaxial layer to provide access to a differently doped buried layer. While suspending the portion of the epitaxial layer surrounded by the trench by means of an oxide bridge, the underl... | 12/19/1989 |
| 4864228 | Electron beam test probe for integrated circuit testing An improved electron beam test probe apparatus and a method for use of said apparatus for use in measuring the potential in a specimen which enables measurements to be insensitive to local electric fields in the vicinity of the point at which the potentia... | 09/05/1989 |
| 4829363 | Structure for inhibiting dopant out-diffusion A method for inhibiting out-diffusion of dopants from polycrystalline or single crystal silicon substrates of high speed semiconductor devices into metal silicide conductive layers disposed on the substrate comprises interposing a refractory metal nitride... | 05/09/1989 |
| 4796080 | Semiconductor chip package configuration and method for facilitating its testing and mounting on a substrate A semiconductor chip package configuration and a method are disclosed for facilitating testing of the chip package and mounting of the chip package on a substrate by forming one or more lead alignment bars in interconnecting relation with adjacent leads o... | 01/03/1989 |
| 4755962 | Microprocessor having multiplication circuitry implementing a modified Booth algorithm A modified Booth algorithm is implemented in the arithmetic logic of the ALU data path to cut the number of cycles to do a multiply in half thereby improving execution time of the multiplication operation. A Booth Encoder examines the two least significan... | 07/05/1988 |
| 4747072 | Pattern addressable memory A memory system for storing and retrieving data sequences of symbols in response to a query sequence is disclosed. Each of the sequences is made up of three types of symbols, constants, delimiters, and variables. A data sequence is retrieved in response t... | 05/24/1988 |
| 4744059 | Apparatus and method for reducing write recovery time in a random access memory An apparatus for reducing the write recovery time of a memory during a write operation is responsive to the detection of a write enable signal for causing the data being written into a selected memory cell to be immediately coupled out on the memory's cor... | 05/10/1988 |
| 4706019 | Electron beam test probe system for analyzing integrated circuits An electron beam test probe system for analyzing the operation of an integrated circuit is described. It includes a circuit for generating a test signal pattern and coupling the test signal pattern to the integrated circuit under test. It also includes an... | 11/10/1987 |
| 4658372 | Scale-space filtering Information indicative discrete events of interest imbedded in raw data are globally classified, or filtered with respect to scale and changes in the scale of observation to effect intelligent perception of phenomena. Large scale components are classified... | 04/14/1987 |
| 4658287 | MOS imaging device with monochrome-color compatibility and signal readout versatility A monochrome or color imager having interlaced, non-interlaced or pseudo-interlaced readout utilizing pixels arranged in groups forming equilateral triangles which are interleaved. Separate vertical shift registers driven by different clock signals to imp... | 04/14/1987 |
| 4627034 | Memory cell power scavenging apparatus and method The present invention utilizes the power available for application to a static RAM cell in a manner which provides efficient use of the power so that greater standby power may be applied to the static RAM to increase the memory speed. The current required... | 12/02/1986 |
| 4543595 | Bipolar memory cell A bipolar memory cell is fabricated by forming diodes 60 and 65 on top of the transistors Q1 and Q2 formed in the underlying substrate 10. Metal silicide 30 overlies strips 34 and 35 of doped polycrystalline silicon 25, 28, 37, and 38 to cross-couple the ... | 09/24/1985 |
| 4542037 | Laser induced flow of glass bonded materials A tunable CO2 gas laser is used to selectively heat various SiO2 -based materials to elevated temperatures while maintaining an active device region at relatively low temperatures, to, for example, induce densification and/or flow of... | 09/17/1985 |
| 4536844 | Method and apparatus for simulating aural response information Speech and like signals are analyzed based on a model of the function of the human hearing system. The model of the inner ear is expressed as signal processing operations which map acoustic signals into neural representations. Specifically, a high order t... | 08/20/1985 |
| 4495382 | Telephone regulator circuitry This invention provides a single integrated circuit device which replaces the non-integrated "encapsulated circuit" of the standard prior art telephone set. The circuit of this invention achieves proper D.C. regulation of the telephone line, by presenting... | 01/22/1985 |
| 4472873 | Method for forming submicron bipolar transistors without epitaxial growth and the resulting structure A vertical bipolar transistor is fabricated in a semiconductor substrate without an epitaxial layer using oxide isolation and ion implantation techniques. Ion implantation energies in the KEV ranges are used to implant selected ions into the substrate to ... | 09/25/1984 |
| 4455325 | Method of inducing flow or densification of phosphosilicate glass for integrated circuits Phosphorus-doped silicon oxide glass is flowed on an integrated circuit by raising the pressure in which that integrated circuit is placed above atmospheric for a selected period of time and heating said phosphosilicate glass to a selected temperature suf... | 06/19/1984 |
| 4451971 | Lift-off wafer processing An improved lift-off process for forming metallized interconnections between various regions on a semi-conductor device relies on the use of a particular polyimide in forming a protective mask over the device. The polyimide is a copolymer of an aromatic c... | 06/05/1984 |
| 4443493 | Laser induced flow glass materials In a semiconductor device, laser energy is used to selectively heat various SiO2 based materials to elevated temperatures while maintaining the active device region and electrical interconnects at relatively low temperatures, to for example, in... | 04/17/1984 |
| 4442449 | Binary germanium-silicon interconnect and electrode structure for integrated circuits An interconnect structure for use in integrated circuits comprises a germanium-silicon binary alloy. Such an alloy is deposited on the semiconductor wafer from the co-deposition of germanium and silicon using chemical vapor deposition techniques of a type... | 04/10/1984 |
| 4435786 | Self-refreshing memory cell A self-refreshing non-volatile memory cell having two cross-coupled transistors includes a first floating gate formed between the gate and the channel of said first transistor, said first floating gate overlying by means of a tunnel oxide a portion of the... | 03/06/1984 |
| 4435790 | High speed, nonvolatile, electrically erasable memory cell and system A method for encoding binary data into an electrically erasable memory. The memory includes a matrix of memory cells formed as a plurality of rows (X write lines/X sense lines/source lines) and columns (Y sense lines) with each cell including a floating g... | 03/06/1984 |
| 4434347 | Lead frame wire bonding by preheating In a method for welding a lead wire or bonding wire from a microcircuit chip mounted on a lead frame to a lead frame finger, the lead frame finger is preheated prior to any substantial electrical or thermal coupling between the lead frame finger and chip.... | 02/28/1984 |
| 4433414 | Digital tester local memory data storage system In a digital tester for evaluating electronic components, a local memory unit for each data channel in the tester is loaded with test vector information only in the locations of the memory relating to transitions that take place in the operation of the da... | 02/21/1984 |
| 4428796 | Adhesion bond-breaking of lift-off regions on semiconductor structures A process is described for removing polyimide regions adhered to the surface of a semiconductor structure 10 which includes the steps of heating the structure 10 and the polyimide regions 12 to between 450° and 490° C., immersing the structure in a solu... | 01/31/1984 |
| 4420365 | Formation of patterned film over semiconductor structure A novel process is disclosed for the selective etching of a protective layer over a substrate according to a predetermined pattern, which does not involve the use of chemical vapor deposition or vacuum techniques. The process incorporates the techniques o... | 12/13/1983 |
| 4420497 | Method of detecting and repairing latent defects in a semiconductor dielectric layer Defects in dielectric layers exhibiting low dielectric strength on silicon substrates (11) are deliberately damaged during manufacture to allow their repair by the formation of dielectric plugs (13B). The defects are damaged by the application of an elect... | 12/13/1983 |
| 4417914 | Method for forming a low temperature binary glass The method of the invention provides a thin film deposit of a binary glass for use in integrated circuits which binary glass has a softening or flow point far below temperatures at which glasses normally used in connection with integrated circuits flow. A... | 11/29/1983 |
| 4415794 | Laser scanning method for annealing, glass flow and related processes A method for scanning the top surface of a semiconductor wafer prevents damage to the wafer (11) by ensuring that the laser beam (13) does not cross over the edge (11a) of the wafer during the scanning process nor approach within one (1) to two (2) millim... | 11/15/1983 |
| 4386420 | Dynamic read reference voltage generator A method and circuitry (5) for enhancing the reproducibility and reliability of circuitry for reading a memory array (10a, 10b, 10a', 10b') provides a dynamically generated reference voltage for the sensing circuitry. The invention senses the highest word... | 05/31/1983 |
| 4384353 | Method and means for internal error check in a digital memory A semiconductor digital memory such as a charge coupled device is provided with error detection capability. Error logic responsive to a group of data on the input bus generates a first error code which is stored in memory along with the group of data. Whe... | 05/17/1983 |
| 4370737 | Sense amplifier and sensing methods A sense amplifier for determining the binary logic state of a dynamic memory cell (11x,y) preamplifies an initial voltage difference established between a first input line (17y) coupled to the memory cell (11x,y) and a fir... | 01/25/1983 |
| 4368420 | Supply voltage sense amplifier A temperature-compensated reference voltage circuit includes a transistor having a positive temperature coefficient of current. A circuit for establishing a predetermined current in the positive-temperature-coefficient-of-current transistor is connected t... | 01/11/1983 |
| 4365332 | Method and circuitry for correcting errors in recirculating memories A method and circuitry are disclosed for correcting bit errors introduced by random events in a data recirculating memory, such as a charge coupled memory device or a bubble memory. The bit errors, caused by random events such as by alpha particle bombard... | 12/21/1982 |
| 4357687 | Adaptive word line pull down An adaptive word line pull-down circuit steers a pull-down current only to the word being pulled down and only for the time when that word is being pulled down. The time that it takes for the bottom word line to fall controls how long the pull-down curren... | 11/02/1982 |
| 4354257 | Sense amplifier for CCD memory A sense amplifier for use with a charge coupled device in which capacitive coupled charge is employed with a flip-flop circuit to accelerate sense and readout. Operation of the amplifier is effected with two external clocks and two internally generated cl... | 10/12/1982 |
| 4352239 | Process for suppressing electromigration in conducting lines formed on integrated circuits by control of crystalline boundary orientation A process for suppressing electromigration in conducting lines formed on integrated circuit structures includes the steps of forming the conducting lines on the integrated circuit structure and heat treating the lines to cause the average grain size in th... | 10/05/1982 |
