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| Number | Title | Issue Date |
| 8115459 | ESR zero estimation and auto-compensation in digitally controlled buck converters One embodiment of the present invention is a digitally controlled DC-DC converter comprising of a power stage including at least one switch and an output capacitor. A digital controller can control the switching of the at least one switch. The digital controller can... | 02/14/2012 |
| 8098090 | Open-drain output buffer for single-voltage-supply CMOS An open-drain output buffer is operative to sustain relatively high voltages applied to an output pad. The open-drain buffer includes a number of floating wells, output switching devices and corresponding well-bias selectors to ensure that no gate oxide sustains vol... | 01/17/2012 |
| 8085024 | Self-tuning digital current estimator for low-power switching converters A switched mode power can use a digital controller to control the switching of the at least one switch of the switched mode power supply. The current through the power inductor can be estimated using a self-tuning digital current estimator. ... | 12/27/2011 |
| 8081041 | Glue-logic based method and system for minimizing losses in oversampled digitally controlled DC-DC converters A practical method and system for oversampled digitally controlled DC-DC converters is presented. To minimize the switching losses while maintaining all advantages of the oversampling, “glue logic” and application specific oversampling digital pulse-width modula... | 12/20/2011 |
| 7969697 | Low-voltage CMOS space-efficient 15 KV ESD protection for common-mode high-voltage receivers An electrostatic discharge protection device is disposed between true-complement input pins of a differential signal pair and a ground node. A common node couples the three diode stacks together. A first and a second diode stack each connect to one of the differenti... | 06/28/2011 |
| 7915938 | Multi-channel digital pulse width modulator (DPWM) A multiple channel Digital Pulse Width Modulator (DPWM) can include a single delay locked loop with a delay line, the delay line producing a number of outputs. Circuitry can use a delay line mask to mask a portion of the delay line outputs to produce a modified outp... | 03/29/2011 |
| 7911366 | Gray code current mode analog-to-digital converter One embodiment of the present invention is a Gray code current-mode analog to digital (ADC) converter using a Gray code current-mode ADC building block. The Gray code current-mode ADC building block can produce a Gray code bit and a current output that is sent to a ... | 03/22/2011 |
| 7908508 | Low power method of responsively initiating fast response to a detected change of condition A voltage signal is monitored in comparison to another voltage signal by a differential amplifier. When the first voltage signal value drops below the second voltage signal value an output signal is boosted in response. The output signal returns to a previous state ... | 03/15/2011 |
| 7908473 | System for storing encrypted data by sub-address A system and method for storing encrypted electronic data using a transmission Control Protocol (TCP), requires leaving both the header and the first 48 bytes of the “0” data packet in the data area of the TCP format in clear text. Consequently, the data can be ... | 03/15/2011 |
| 7902874 | Combined full speed and high speed driver The separate high speed and full speed drivers used in a Universal Serial Bus 2.0 application can be combined into one driver which functions both as full speed/high speed driver and as a result provides output impedance for the full speed/high speed modes which is ... | 03/08/2011 |
| 7873045 | Generating an encapsulating header based on encapsulated information provided at protocol-dependent locations An encapsulation packet is received as a sequence of parallel data segments. First information within the encapsulated packet is obtained based on second information indicative of a location of the first information within the encapsulated packet. The encapsulating ... | 01/18/2011 |
| 7834672 | Low power charge pump A charge pump is configured to control current flow at an output node in response to input signals. A plurality of control signals are generated based upon the input signals. The control signals operate to control the timing and duration of current flows within the ... | 11/16/2010 |
| 7821431 | Universal and fault-tolerant multiphase digital PWM controller for high-frequency DC-DC converters A multiphase hybrid digital pulse width modulator can comprise a counter that is selectable between at least two different numbers of states to indicate a first portion of a switching period. Unclocked logic can indicate a second portion of the switching period. The... | 10/26/2010 |
| 7816958 | Means to reduce the PLL phase bump caused by a missing clock pulse A PLL includes control circuitry adapted to detect missing pulses of a reference clock and to control an output voltage of a charge pump disposed in the PLL accordingly. A signal generated in response to the detection of a missing pulse is pulse-width limited and ap... | 10/19/2010 |
| 7814376 | Method and apparatus for frame delineation A frame delineation mechanism which alternately considers even and odd sync pattern position possibilities. With the addition of toggle logic, each of 66 possible states of even and odd alignment are exhausted in turn, odd, followed by even, followed by odd and so o... | 10/12/2010 |
| 7773357 | Auto-detecting CMOS input circuit for single-voltage-supply CMOS An auto-detecting input circuit is operative to sustain relatively high voltages applied to an input pad and generate corresponding signal levels at a native supply voltage range. The input circuit includes floating wells, corresponding bias selectors, and input bia... | 08/10/2010 |
| 7760015 | Combination offset voltage and bias current auto-zero circuit A circuit with an input acquisition loop and an output acquisition loop is used to compensate for the input offset voltage and bias current errors of an operational amplifier. ... | 07/20/2010 |
| 7710209 | Digital pulse frequency/pulse amplitude (DPFM/DPAM) controller for low-power switching-power supplies A digital controller for dc-dc switching converters can operate under light load conditions. The controller can be suitable for the use in switch-mode power supplies providing regulated output voltage for handheld devices and other low-power electronics. To create l... | 05/04/2010 |
| 7710174 | Digital pulse-width modulator based on non-symmetric self-oscillating circuit A low-power digital pulse-width modulator (DPWM) architecture for high frequency dc-dc switch-mode power supplies (SMPS) is disclosed that is well-suited for integration in power management systems of small handheld devices. The DPWM can operate in a stand-alone mod... | 05/04/2010 |
| 7701976 | Communications system with segmenting and framing of segments A communications system comprising a segmenting mechanism configured to receive a plurality of payloads and divide each of the received payloads into segments, a framing mechanism configured to insert at least one of the segments from each of the plurality of payloa... | 04/20/2010 |
| 7696912 | Interrupt based multiplexed current limit circuit A switching voltage regulator includes, in part, N output stages, a loop ADC, a multiplexer, a current ADC, and an interrupt block. The loop analog-to-digital converter receives the N output voltages each of which is associated with one of N channels. The loop ADC i... | 04/13/2010 |
| 7688154 | Amplitude regulated crystal oscillator To maintain the amplitude of an oscillating signal within a defined range, the detected peak level of the oscillating signal is compared to a reference voltage. If the detected peak level is determined as being greater than the reference voltage, the common source/d... | 03/30/2010 |
| 7683696 | Open-drain output buffer for single-voltage-supply CMOS An open-drain output buffer is operative to sustain relatively high voltages applied to an output pad. The open-drain buffer includes a number of floating wells, output switching devices and corresponding well-bias selectors to ensure that no gate oxide sustains vol... | 03/23/2010 |
| 7667625 | Universal and fault-tolerant multiphase digital PWM controller for high-frequency DC-DC converters A multiphase hybrid digital pulse width modulator can comprise a counter that is selectable between at least two different numbers of states to indicate a first portion of a switching period. Unclocked logic can indicate a second portion of the switching period. The... | 02/23/2010 |
| 7652604 | Programmable analog-to-digital converter for low-power DC-DC SMPS A voltage-to-time based windowed analog-to-digital converter (ADC) can have programmable reference voltage, conversion time, and accuracy of voltage regulation. The ADC can be fully implemented on a small silicon area and is suitable for implementation in various in... | 01/26/2010 |
| 7646224 | Means to detect a missing pulse and reduce the associated PLL phase bump A phase/frequency locked loop (PLL) includes circuitry adapted to detect missing pulses of a reference clock and to control the phase bump of the PLL. The circuitry includes, in part, first and second flip-flops, as well as a one-shot block. The first flip-flop has ... | 01/12/2010 |
| 7620030 | Method and apparatus for terminating/generating physically and virtually concatenated signals A SONET signal is terminated by pointer processing a physically concatenated SONET signal to output a pointer processed physically concatenated SONET signal. Virtual concatenation-related byte markers (for example, H4 and J1) are then inserted into the pointer proce... | 11/17/2009 |
| 7609185 | Methods of using predictive analog to digital converters Methods are disclosed for performing analog to digital signal conversion in shorter time and/or with less power consumption. A predictive guess is supplied as a digital first signal. The digital first signal is converted (D/A) to a counterpart, analog guess signal. ... | 10/27/2009 |
| 7590130 | Communications system with first and second scan tables A communications system comprising a first stage including a first scan table and a second stage including a second scan table. The first stage is configured to select a first channel identification from the first scan table and provide data from a channel identifie... | 09/15/2009 |
| 7589704 | Smart talk backlighting system and method A smart talk mechanism provides feedback information from a driver to a DC-to-DC converter, enabling the DC-to-DC converter to adjust an input voltage for at least one illumination source backlighting the display for increasing the power efficiency. ... | 09/15/2009 |
| 7574321 | Model predictive thermal management Electrical components which substantially dissipate the power provided them in the form of heat will change temperature in response to self heating, heat transfer to their surroundings, and heat transferred from one component to another. A method is disclosed for ca... | 08/11/2009 |
| 7543163 | Low power method of monitoring and of responsively initiating higher powered intelligent response to detected change of condition A synchronous control system includes a logic controller (e.g., microprocessor) which can be put into low power standby or sleep mode by shutting off its clock. A quick-start oscillator (QSO) remains shut off to conserve power when not needed, but awakens rapidly an... | 06/02/2009 |
| 7528571 | Method for charging a battery using a constant current adapted to provide a constant rate of change of open circuit battery voltage A method for charging a battery is disclosed, wherein a constant current charging current is periodically adjusted as needed such that the change in battery voltage increases approximately linearly during the charging period. In some embodiments the charging is in t... | 05/05/2009 |
| 7525471 | Wide-input windowed nonlinear analog-to-digital converter for high-frequency digitally controlled SMPS In embodiments, a new analog-to-digital converter (ADC) architecture can be used with switch-mode power supplies (SMPS) operating at switching frequencies higher than 10 MHz. Analog-to-digital converter embodiments can achieve very low power consumption, fast conver... | 04/28/2009 |
| 7459951 | Self-calibrating digital pulse-width modulator (DPWM) A hybrid digital pulse width modulator can have a delay line with digitally programmable delay cells. The digitally programmable delay cells can be adjusted by a digital correction signal from a delay matching circuit. ... | 12/02/2008 |
| 7457335 | Fast loop laser diode driver A laser diode driver circuit can comprise fast loop portion and a closed-loop portion. The closed-loop driver portion can provide a part of the current for a laser diode. The closed-loop drive portion output can be independent of a photodetector. The fast-loop drive... | 11/25/2008 |
| 7441039 | Method and apparatus for adapting mac and network processor core to packet format changes and for mapping RPR architecture over spatial reuse architecture A data communications device that can operate in accordance with two or more protocols having different data formats and error-protection schemes. The protocol-dependent aspects of the device are handled by a peripheral portion of the device, allowing a substantiall... | 10/21/2008 |
| 7436245 | Variable sub-bandgap reference voltage generator A sub-bandgap reference voltage generator, generates a pair of variable voltages one having a positive temperature coefficient and one having a negative voltage coefficient. The pair of voltages are added to generate an output voltage whose value and temperature may... | 10/14/2008 |
| 7411460 | Elimination of dummy detector on optical detectors using input common mode feedback A voltage reference forces a constant voltage at the inputs to an amplifier, thereby negating a need for a dummy detector on the non-active input of the amplifier. ... | 08/12/2008 |
| 7411426 | Phase detector for RZ A phase detector is adapted to receive first and second signals and generate third and fourth signals representative of the difference between the phases of the first and second signals. The phase detector assert the third signal in response to the assertion of the ... | 08/12/2008 |
