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| Number | Title | Issue Date |
| 6320735 | Electrostatic discharge protection clamp for high-voltage power supply or I/O with nominal-or high-voltage reference An electrostatic discharge (ESD) protection technique protects a semiconductor device against electrostatic discharge events. The technique uses an ESD protection circuit that includes Darlington-connected clamps between the protected I/O pad and a refere... | 11/20/2001 |
| 6195377 | Embedded input logic in a high input impedance strobed CMOS differential sense amplifier The present invention provides a sense amplifier that incorporates a logic function. Specifically, that logic function is incorporated into the sense amplifier such that the propagation time of the logic function is avoided and the effective data set-up t... | 02/27/2001 |
| 6173287 | Technique for ranking multimedia annotations of interest A technique for accessing an item of interest within a particular one of a plurality of stored representations of data is disclosed. In one embodiment, the technique is realized by having a processing device searching a plurality of stored annotations cor... | 01/09/2001 |
| 6134642 | Direct memory access (DMA) data transfer requiring no processor DMA support A digital system has a main memory 10 with a main memory access (DMA) unit 11 through which data channels 12, 13 are coupled to the memory. A processor system (processor 14, RAM data memory 15, instruction memory 16) is also coupled to the memory through ... | 10/17/2000 |
| 6133717 | Methods and apparatus for synchronizing a plurality of power supplies A technique involves broadcasting a pulse signal to synchronize oscillating signals used by multiple power supplies to provide output voltages. The technique involves charging and discharging respective capacitors of the multiple power supplies at respect... | 10/17/2000 |
| 6131107 | Fast determination of carry inputs from lower order product for radis-8 odd/even multiplier array A multiplier in a floating point processor includes a circuit to determine for each bit of the multiplier operand a 3 times booth recode and a booth recode multiplier array which implements a 3 times booth recode multiplication. The multiplier includes lo... | 10/10/2000 |
| 6131150 | Scaled memory allocation system A memory of a computer system is partitioned into a plurality of allocable blocks. Subsets of the allocable blocks are organizing into a plurality of heaps, each heap having a different designated subset of the allocable blocks. The sizes of the allocable... | 10/10/2000 |
| 6119075 | Method for estimating statistics of properties of interactions processed by a processor pipeline Provided is a method for estimating statistics of properties of interactions among instructions processed in a pipeline of a computer system, the pipeline having a plurality of processing stages. Instructions are fetched into a first stage of the pipeline... | 09/12/2000 |
| 6108770 | Method and apparatus for predicting memory dependence using store sets A method of scheduling program instructions for execution in a computer processor comprises fetching and holding instructions from an instruction memory and executing the fetched instructions out of program order. When load/store order violations are dete... | 08/22/2000 |
| 6101516 | Normalization shift prediction independent of operand subtraction A pipelined floating point processor including an add pipe for performing floating point additions is described. The add pipe includes a circuit to predict a normalization shift amount from examination of input operands, a circuit to determine the "Sticky... | 08/08/2000 |
| 6091897 | Fast translation and execution of a computer program on a non-native architecture by use of background translator A computer system for executing a binary image conversion system which converts instructions from a instruction set of a first, non native computer system to a second, different native computer system, includes an run-time system which in response to a no... | 07/18/2000 |
| 6092101 | Method for filtering mail messages for a plurality of client computers connected to a mail service system A computer implemented method for filtering mail messages in a distributed computer system. The distributed mail service system includes a plurality of client computers connected to a mail service system via a network. Mail messages are stored in message ... | 07/18/2000 |
| 6085292 | Apparatus and method for providing non-blocking pipelined cache A cache includes an address cache for storing memory addresses. An address queue is connected to the address cache for storing missed addresses in the order that the address cache is probed. A memory controller receives the missed addresses from the addre... | 07/04/2000 |
| 6078565 | Method and apparatus to expand an on chip FIFO into local memory A relatively small FIFO queue is located on a semiconductor chip receiving and transmitting data in a computer system, typically a computer network. The FIFO queue has additional storage capability in the form of an expansion into the local memory of the ... | 06/20/2000 |
| 6076158 | Branch prediction in high-performance processor A CPU of the RISC type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes limited to register-to-register operations and register load/store operations. Byte manipulation instructions ... | 06/13/2000 |
| 6076129 | Distributed data bus sequencing for a system bus with separate address and data bus protocols A data bus sequencer for use by nodes coupled to a system bus for associating data transactions and address transactions on the bus. The data bus sequencer includes means for tracking address and command transactions occurring on an address bus, the means... | 06/13/2000 |
| 6075704 | Input/output bus system in a tower building block system In a modular tower building block system for containing computing system devices, an I/O bus is incorporated into the modular blocks of the building block system by using a printed circuit board to carry the I/O bus in each modular block. The printed circ... | 06/13/2000 |
| 6076176 | Encoding of failing bit addresses to facilitate multi-bit failure detect using a wired-OR scheme A technique for encoding failing bit addresses in a memory array with redundant portions such as column slices. The address or other identification of a column slice or other portion of a memory array is identified to test logic using a wired-OR bus confi... | 06/13/2000 |
| 6061773 | Virtual memory system with page table space separating a private space and a shared space in a virtual memory A virtual memory system includes a virtual address space including a process private space, a shared space, and a page table space located between the process private space and the shared space. The page table space includes page table entries mapping bot... | 05/09/2000 |
| 6061686 | Updating a copy of a remote document stored in a local computer system In response to a command by a local computer system, a copy of a remote document is downloaded onto a remote update network device from an origin network device. A predetermined time after the remote document copy is downloaded, the update network device ... | 05/09/2000 |
| 6052706 | Apparatus for performing fast multiplication In accordance with the present invention a circuit for performing an iterative process on a data stream is provided. The iterative process includes pipeline stages which operate on a portion of the data stream to produce an output which is an input to a s... | 04/18/2000 |
| 6047078 | Method for extracting a three-dimensional model using appearance-based constrained structure from motion In a computerized method, a three-dimensional model is extracted from a sequence of images that includes a reference image. Each image in the sequence is registered with the reference image to determine image features. The image features are used to recov... | 04/04/2000 |
| 6038689 | Fault notification system and process using local area network A fault notification system detects the non-operational state of the computer, or other type of network device, and transmits network messages from the device to a monitoring system or control console in the case of a detected non-operational state. The n... | 03/14/2000 |
| 6031539 | Facial image method and apparatus for semi-automatically mapping a face on to a wireframe topology A method for mapping a digitized image of a face on to a reference wireframe topology in a computer system is provided, the image composed of pixels, the wireframe composed of interconnected nodes, the method including the steps of determining facial feat... | 02/29/2000 |
| 6025745 | Auto-calibrating digital delay circuit A delay circuit comprises a tapped delay element line constructed from delay elements with fixed delay intervals and a multiplexer for selecting the signal at one of the taps to produce a variable delay through the circuit. The multiplexer is controlled b... | 02/15/2000 |
| 6026475 | Method for dynamically remapping a virtual address to a physical address to maintain an even distribution of cache page addresses in a virtual address space A method and apparatus for dynamically updating virtual to physical address mappings in order to reduce cache thrashing is disclosed in an example computer system having a memory apportioned into a number of pages. A cache is included in the computer syst... | 02/15/2000 |
| 6018771 | Dynamic assignment of multicast network addresses Multicast addresses on a computer network are dynamically assigned to a temporary node task. In particular, a server dynamically assigns a multicast address to a data stream in response to a request for the data stream from a client. The server assigns th... | 01/25/2000 |
| 6016467 | Method and apparatus for program development using a grammar-sensitive editor Techniques used in program development using a grammar sensitive editor are described. Input within an edit buffer is processed by a lexical and syntax analyzer in response to various syntactic and lexical states. Actions such as updating various multimed... | 01/18/2000 |
| 6016148 | Automated mapping of facial images to animation wireframes topologies A method for mapping a digitized image of a face to a wireframe is provided. The wireframe is composed of a plurality of nodes connected by lines. The method includes the steps of detecting a plurality of facial features from the plurality of pixels of a ... | 01/18/2000 |
| 6016529 | Memory allocation technique for maintaining an even distribution of cache page addresses within a data structure In a computer system, a data structure is provided in memory for storing one or more data files from an external device. The data files stored in the data structure are accessible by a number of processes executing in the computer system. The computer sys... | 01/18/2000 |
| 6014690 | Employing multiple channels for deadlock avoidance in a cache coherency protocol An architecture and coherency protocol for use in a large SMP computer system includes a hierarchical switch structure which allows for a number of multi-processor nodes to be coupled to the switch to operate at an optimum performance. Within each multi-p... | 01/11/2000 |
| 6012074 | Document management system with delimiters defined at run-time A document management apparatus provides a user to define delimiters in order to specify portions of documents or attributes of documents to be retrieved from a document repository. The repository is searched for the defined delimiters and the portions of... | 01/04/2000 |
| 6012072 | Display apparatus for the display of documents in a three-dimensional workspace An apparatus for displaying documents on a computer controlled display device provides a method for clipping. To clip a document is to restrict the viewable area of the screen object on the computer controlled display device associated with the document. ... | 01/04/2000 |
| 6011299 | Apparatus to minimize integrated circuit heatsink E.M.I. radiation A set of conductive plates are positioned adjacent to and in close proximity with a unidirectional heatsink on a high frequency integrated circuit. The set of plates is generally electrically attached to the same ground potential voltage supply as the int... | 01/04/2000 |
| 6011679 | Methods and apparatus for controlling a power supply with improved techniques for providing protection limits A technique for controlling a power supply involves receiving a programming signal that indicates a power supply output voltage limit, activating the power supply such that the power supply provides a power supply output voltage according to a power suppl... | 01/04/2000 |
| 6012120 | Method and apparatus for providing DMA transfers between devices coupled to different host bus bridges A multiprocessor having improved bus efficiency is shown to include a number of processing units and a memory coupled to a system bus. Also coupled to the system bus are at least one I/O bridge systems. A method for improving partial cache line writes fro... | 01/04/2000 |
| 6009521 | System for assigning boot strap processor in symmetric multiprocessor computer with watchdog reassignment A boot strap assignment system is disclosed for a symmetric multiprocessor computer in which the role of the boot strap processor is assigned to one of the working processors by a central agent as part of power-on configuration. The system includes a syst... | 12/28/1999 |
| 6009514 | Computer method and apparatus for analyzing program instructions executing in a computer system In a computerized method, performance data collected while a computer system executed instructions of a program are analyzed. The method collects performance data while executing the program. The performance data includes sample counts of instructions exe... | 12/28/1999 |
| 5999737 | Link time optimization via dead code elimination, code motion, code partitioning, code grouping, loop analysis with code motion, loop invariant analysis and active variable to register analysis A computer system is directed to convert a program written as a plurality of high level source code modules into corresponding machine executable code. The source code modules are compiled into an object code module, and the object code modules are transl... | 12/07/1999 |
| 6000028 | Means and apparatus for maintaining condition codes in an unevaluated state A computer system for executing a binary image conversion system which converts instructions from a instruction set of a first, non native computer system to a second, different, native computer system, includes an run-time system which in response to a n... | 12/07/1999 |
