Celebrity Inventors
Glam girl Heddy Lamar may have used her good looks to good effect on the silver screen, but she put her smarts to better use as an inventor. During World War II, she co-patented a frequency-switching system for torpedo guidance that was considered years ahead of its time.
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| Number | Title | Issue Date |
| 6324692 | Upgrade of a program A method and processor program product for performing an upgrade of a program on a processor are provided. An upgraded version of the program is received into the processor and a backup of the program is created in memory associated with the processor. Th... | 11/27/2001 |
| 6122756 | High availability computer system and methods related thereto A high availability computer system and methodology including a backplane, having at least one backplane communication bus and a diagnostic bus, a plurality of motherboards, each interfacing to the diagnostic bus. Each motherboard also includes a memory s... | 09/19/2000 |
| 6026461 | Bus arbitration system for multiprocessor architecture A very fast, memory efficient, highly expandable, highly efficient CCNUMA processing system based on a hardware architecture that minimizes system bus contention, maximizes processing forward progress by maintaining strong ordering and avoiding retries, a... | 02/15/2000 |
| 6021044 | Heatsink assembly A heatsink assembly for removing at least some of the heat produced by an electronic component during use includes a heatsink, a heatpipe mounted on the heatsink and a plurality of thin, elongated fins mounted on the heatpipe. The heatsink is an elongated... | 02/01/2000 |
| 6014009 | Electronic device An electronic device supplied power from either a single rechargeable battery or four non-rechargeable batteries. The single rechargeable battery is preferably a 4.8 volt, DURACELL DR-121 rechargeable battery which includes a first end having positive and... | 01/11/2000 |
| 5956754 | Dynamic shared user-mode mapping of shared memory A method for use in a multiprocessor computer system where data objects larger than the address space of a single task are mapped in main memory and the translation lookaside buffer (TLB) is maintained by user mode software is disclosed. The method uses l... | 09/21/1999 |
| 5937159 | Secure computer system A system and method for controlling the access of users to a trusted computer system using an authentication and authorization database, containing information used to authenticate human users and information establishing what each user can do, and a numb... | 08/10/1999 |
| 5922077 | Fail-over switching system A recovery method and fail-over switch for use in a data storage system in which a plurality of data storage devices are connected to each of two communication paths. The switch may route requests to either of the two communication paths. Switching may be... | 07/13/1999 |
| 5911150 | Data storage tape back-up for data processing systems using a single driver interface unit A technique for handling tape back-up data storage systems for use with a data processing system, wherein a single tape driver interface unit has a process controller for controlling access to an array of tape drive units and data storage tapes. Data is t... | 06/08/1999 |
| 5901151 | System for orthogonal signal multiplexing A high frequency signal and a low frequency signal are coupled onto a pair of conductors providing a communication link between two computer components. The high frequency signal may be a differentially coupled Fibre Channel 8B/10B encoded signal. A diple... | 05/04/1999 |
| 5890214 | Dynamically upgradeable disk array chassis and method for dynamically upgrading a data storage system utilizing a selectively switchable shunt A dynamically upgradeable disk array chassis, and a method for dynamically upgrading a data storage system. The dynamically upgradeable disk array chassis includes a serial bus having a first bus for passing data in one direction and a second bus for pass... | 03/30/1999 |
| 5889934 | Data validation system for a group of data storage disks In an array of data storage disks, a data validation system for data arranged in corresponding sectors of a sector group that includes a parity sector. Each user data sector in a sector group is assigned at least two of a plurality of validation fields fo... | 03/30/1999 |
| 5887146 | Symmetric multiprocessing computer with non-uniform memory access architecture A very fast, memory efficient, highly expandable, highly efficient CCNUMA processing system based on a hardware architecture that minimizes system bus contention, maximizes processing forward progress by maintaining strong ordering and avoiding retries, a... | 03/23/1999 |
| 5878248 | Device access controller for virtual video/keyboard/mouse input/output for remote system management and maintenance A device access controller residing in a first computer system for transferring virtual inputs and outputs representing operations of the first system between the first system and a second system. The device access controller includes a video controller f... | 03/02/1999 |
| 5861737 | Soft-start switch with voltage regulation and current limiting A MOSFET, an op-amp, a comparator circuit, and voltage dividers with capacitors are employed in combination to effectuate a soft-start switch with current limiting. The transconductance of the MOSFET is employed so that no sense resistor is required. The ... | 01/19/1999 |
| 5860139 | BIOS memory address decoder for providing an extended BIOS memory address space by reclaiming a portion of non-BIOS address space A BIOS address decoder for addressing an extended BIOS memory for storing additional microprograms in a computer system. A system component is connected from the bus for receiving program instruction addresses in a first address range and providing corres... | 01/12/1999 |
| 5859966 | Security system for computer systems A security system for a computer system imposes specific limitations on who has access to the computer system and to exactly what operations and data. Viruses are securely contained and prevented from expanding into areas where they can destroy stored pro... | 01/12/1999 |
| 5860098 | Process for running a computer program subject to interrupt A data processing system and method of operation which substantially reduces the time lost in unnecessarily checking for the presence of all memory references required by a special section of code in an operating system before the program is run and which... | 01/12/1999 |
| 5845094 | Device access controller and remote support facility for installation of cabling in a multiprocessor system A support facility for installation of interprocessor unit cabling interconnecting the processor units of a multiple processor unit system in a first network, including a second system for directing the cabling interconnections of the first system and, in... | 12/01/1998 |
| 5809256 | Soft power switching for hot installation and removal of circuit boards in a computer system A soft power switch for insertion and removal of a logic unit in a system during continuing operation of the system, including a current switch for each supply voltage to the logic unit that is to be protected, each current switch having a current input c... | 09/15/1998 |
| 5806086 | Multiprocessor memory controlling system associating a write history bit (WHB) with one or more memory locations in controlling and reducing invalidation cycles over the system bus A memory controller system for use with a plurality of processor nodes capable of reducing the number of invalidate cycles on a shared system bus in cache coherent non-uniform memory architecture multiprocessor by detecting when a memory block is being up... | 09/08/1998 |
| 5787468 | Computer system with a cache coherent non-uniform memory access architecture using a fast tag cache to accelerate memory references A fast tag cache is an array to cache a limited set of identifiers specifying the residency and access rights to memory blocks and cache blocks contained in a node within a distributed memory system built using a cache coherent non-uniform memory access a... | 07/28/1998 |
| 5745778 | Apparatus and method for improved CPU affinity in a multiprocessor system Closely related processing threads within a process in a multiprocessor system are collected into thread groups which are globally scheduled as a group based on the thread group structure's priority and scheduling parameters. The thread group structure ma... | 04/28/1998 |
| 5713004 | Cache control for use in a multiprocessor to prevent data from ping-ponging between caches A multiprocessor cache control uses ping-pong bits to reduces the number of invalidate cycles on a shared system bus in a multiprocessor system with a plurality of caches when data is being updated by multiple CPUs. The ping-pong bit is used predict when ... | 01/27/1998 |
| 5698973 | Soft-start switch with voltage regulation and current limiting A MOSFET, an op-amp, a comparator circuit, and voltage dividers with capacitors are employed in combination to effectuate a soft-start switch with current limiting. The transconductance of the MOSFET is employed so that no sense resistor is required. The ... | 12/16/1997 |
| 5687089 | Drive regulator circuit board for a 3.50 inch disk drive A drive regulator circuit board for use with a 3.50 inch disk drive unit. The drive regulator circuit board includes a regulator section for receiving +24 volts distributed power and providing therefrom regulated +5V and +12V DC power, a monitor circuit f... | 11/11/1997 |
| 5686814 | Battery circuit for supplying power to an electronic device A battery circuit for use in supplying power to an electronic device comprises a first battery source, a second battery source connected in parallel to the first battery source, a first auxiliary circuit for preventing the first battery source from being ... | 11/11/1997 |
| 5684973 | Expandable memory system and method for interleaving addresses among memory banks of different speeds and sizes An expandable memory system and a method for operating a memory system having a variable number of memory banks are described. The memory system can utilize a variable number of separately replaceable memory banks which can be implemented with memory elem... | 11/04/1997 |
| 5666486 | Multiprocessor cluster membership manager framework A shared-disk cluster system includes a cluster membership manager framework which coordinates the joining or leaving among all nodes in a cluster including taking the multiple layers of involved subsystems through transitions. Subsystems are notified of ... | 09/09/1997 |
| 5617558 | Method of executing a series of computer code operations that must be completed without interruption by a page fault during execution The time lost in unnecessarily checking for the presence of all memory references required by a special section of code in an operating system before the program is run and which dynamically protects the program requiring the memory reference from crashin... | 04/01/1997 |
| 5535381 | Apparatus and method for copying and restoring disk files A method and apparatus for backing up files from a logical disk are described to a backup tape and restoring all or part of the files to the logical disk. Separate "backup" and "copy" buffers in the host processor's main memory are employed during a backu... | 07/09/1996 |
| 5490723 | Disk array subsystem for use in a data processing system A disk drive module adapted for use in a data processing system, the system including first and second disk drive module guide plates. The disk drive module comprises an elongated, generally rectangular frame. The top wall of the frame includes a fin slid... | 02/13/1996 |
| 5481681 | Data transfer operations between two asynchronous buses A technique for permitting data transfers between a high speed bus and a low speed bus which operate independently and asynchronously wherein when the low speed bus requires access to the high speed bus, the busy status of the latter bus is determined and... | 01/02/1996 |
| 5452444 | Data processing system using fligh availability disk arrays for handling power failure conditions during operation of the system A method for handling data in a plurality of data storage disks having user data sectors and corresponding parity sectors, the method being used when the disks are being operated in a non-degraded or a degraded mode wherein a non-volatile RAM is used in a... | 09/19/1995 |
| 5450592 | Shared resource control using a deferred operations list A method for handling attempts by multiple processing threads to access a shared system resource is disclosed. When a thread attempts to access a locked resource, the thread creates a description of the operation it intended to perform and stores the desc... | 09/12/1995 |
| 5396111 | Clocking unit for digital data processing A technique for generating gated clock signals for use in enabling various operating gating units in a data processing system in which an internal reference clock signal is used to generate both processor clock signals and the gated clock signals such tha... | 03/07/1995 |
| 5388232 | Method and system for providing successive data transfers among data processing units in a non-multiplexed asynchronous manner using unique pipelined arbitration, address, and data phase operations A method for performing address and data transfers among a plurality of different units of a data processing system having a system bus which includes an address bus and a data bus. The system uses arbitration phase, address transfer phase, and data trans... | 02/07/1995 |
| 5377332 | Bus arbitration algorithm and apparatus A bus arbitration algorithm using round robin and variable packet counts. In addition, each node is assigned a maximum packet size which can be adjusted by the operating system. The round robin determines which node will be granted the bus based on priori... | 12/27/1994 |
| 5377328 | Technique for providing improved signal integrity on computer systems interface buses An interface system for transmitting a pulse waveform signal between a host computer and a plurality of peripheral units wherein such signal is transmitted on a dedicated bus, the peripheral units being connected to the bus in selected groups thereof. Eac... | 12/27/1994 |
| 5377191 | Network communication system In a network communication system passing messages between gateways via a message handling system the gateways are interfaced specifically to their respective network access units and are interfaced generically to the message handling system using routine... | 12/27/1994 |
