Assignee: DSM Solutions, Inc.

Location: Los Gatos, CA
No. of patents: 19

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Number	Title	Issue Date
7694069	System and method for detecting multiple matches A system for identifying asserted signals includes a plurality of input ports, a priority encoding module, and a match module. The plurality of input ports receive one of a plurality of input signals. The priority encoding module is coupled to the plurality of input...	04/06/2010
7648898	Method to fabricate gate electrodes A method for fabricating a semiconductor device comprises depositing a first layer of oxide on at least a portion of a channel of a transistor. The method further comprises depositing a layer of nitride on the first layer of oxide and etching at least a portion of t...	01/19/2010
7646233	Level shifting circuit having junction field effect transistors A level shifting circuit can include a first driver junction field effect transistor (JFET) having a source coupled to a reference supply node and a second driver JFET of a second conductivity type having a source coupled to a boosted supply node, and a first charge...	01/12/2010
7645662	Transistor providing different threshold voltages and method of fabrication thereof A transistor includes a channel region with a first portion and a second portion. A length of the first portion is smaller than a length of the second portion. The first portion has a higher threshold voltage than the second portion. The lower threshold voltage of t...	01/12/2010
7645654	JFET with built in back gate in either SOI or bulk silicon A process for manufacturing a Junction Field-Effect Transistor, comprises doping a semiconductor material formed on an insulating substrate with impurities of a first conductivity type to form a well region. The process continues by implanting impurities of a second...	01/12/2010
7642566	Scalable process and structure of JFET for small and decreasing line widths A scalable device structure and process for forming a normally off JFET with 45 NM linewidths or less. The contacts to the source, drain and gate areas are formed by forming a layer of oxide of a thickness of less than 1000 angstroms, and, preferably 500 angstroms o...	01/05/2010
7633784	Junction field effect dynamic random access memory cell and content addressable memory cell A semiconductor memory device including a dynamic random access memory (DRAM) cell and a ternary content addressable memory (TCAM) cell is disclosed. The DRAM cell may include a data storing portion and a data read portion. The data storing portion and data read por...	12/15/2009
7633101	Oxide isolated metal silicon-gate JFET A JFET structure with self-aligned metal source, drain and gate contacts with very low resistivity and very small feature sizes. Small source, drain and gate openings are etched in a thin dielectric layer which has a thickness set according to the desired source, ga...	12/15/2009
7629812	Switching circuits and methods for programmable logic devices A switching circuit can have a plurality of first signal lines of a programmable logic device, a plurality of second signal lines of the programmable logic device, and a plurality of switch elements. Each switch element can selectively couple one first signal line t...	12/08/2009
7605031	Semiconductor device having strain-inducing substrate and fabrication methods thereof A semiconductor device includes a semiconductor substrate that includes a substrate layer having a first composition of semiconductor material. A source region, drain region, and a channel region are formed in the substrate, with the drain region spaced apart from t...	10/20/2009
7592841	Circuit configurations having four terminal JFET devices Circuits using four terminal junction field effect transistors (JFETs) are disclosed. Such circuits can include various static and dynamic logic circuits, flip-flops, multiplexer, tri-state driver, phase detector, logic having variable speeds of operation, and/or an...	09/22/2009
7569873	Integrated circuit using complementary junction field effect transistor and MOS transistor in silicon and silicon alloys This invention describes a method of building complementary logic circuits using junction field effect transistors in silicon. This invention is ideally suited for deep submicron dimensions, preferably below 65 nm. The basis of this invention is a complementary Junc...	08/04/2009
7560755	Self aligned gate JFET structure and method A JFET integrated onto a substrate having a semiconductor layer at least and having source and drain contacts over an active area and made of first polysilicon (or other conductors such as refractive metal or silicide) and a self-aligned gate contact made of second ...	07/14/2009
7557393	JFET with built in back gate in either SOI or bulk silicon A Junction Field-Effect transistor with no surface contact for the back gate and twice as much transconductance in the channel and with a higher switching speed is achieved by intentionally shorting the channel-well PN junction with the gate region. This is achieved...	07/07/2009
7531854	Semiconductor device having strain-inducing substrate and fabrication methods thereof A semiconductor device includes a semiconductor substrate that includes a substrate layer having a first composition of semiconductor material. A source region, drain region, and a channel region are formed in the substrate, with the drain region spaced apart from t...	05/12/2009
7525163	Semiconductor device, design method and structure A semiconductor device can include at least a first diffusion region formed by doping a semiconductor substrate and at least a second diffusion region formed by doping the semiconductor substrate that is separated from the first diffusion region by an isolation regi...	04/28/2009
7525138	JFET device with improved off-state leakage current and method of fabrication A junction field effect transistor comprises a semiconductor substrate. A first impurity region of a first conductivity type is formed in the substrate. A second impurity region of the first conductivity type is formed in the substrate and spaced apart from the firs...	04/28/2009
7525136	JFET device with virtual source and drain link regions and method of fabrication A junction field effect transistor comprises a semiconductor substrate. A source region of a first conductivity type is formed in the substrate. A drain region of the first conductivity type is formed in the substrate. A channel region of the first conductivity type...	04/28/2009
7474125	Method of producing and operating a low power junction field effect transistor A method for using an inverter with a pair of complementary junction field effect transistors (CJFET) with a small linewidth is provided. The method includes having an input capacitance for said CJFET inverter to be less than the corresponding input capacitance of a...	01/06/2009

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Assignee: DSM Solutions, Inc.