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| Number | Title | Issue Date |
| 7459671 | Two-dimensional motion sensor An optical sensor and method of using the same is provided for sensing relative movement between the sensor and a surface by detecting changes in optical features of light reflected from the surface. In one embodiment, the sensor includes a two dimensional array of ... | 12/02/2008 |
| 7447958 | Parallel input/output self-test circuit and method A parallel data transmission test system can include a receiver section (100) having input selector circuits (104-O to 104-N) that provide a received test data to logic adjust circuits (106-O to 106-N) that “logically align” mu... | 11/04/2008 |
| 7446805 | CMOS active pixel with hard and soft reset A circuit for a pixel site in an imaging array includes a light-detecting element to convert incident light to a photocurrent and a reset transistor, operatively connected to the light-detecting element, to reset a voltage associated with the light-detecting element... | 11/04/2008 |
| 7439816 | Phase-locked loop fast lock circuit and method Phase-locked loop fast lock circuit and method are described. The apparatus including a voltage controlled oscillator, a control loop filter having a capacitor and at least one resistor, and first and second control elements coupled with the control loop filter. The... | 10/21/2008 |
| 7439812 | Auto-ranging phase-locked loop A phase locked loop circuit includes an oscillator, a dividing circuit coupled to the oscillator having a controllable dividing factor, and a rangefinder circuit coupled to the dividing circuit. The rangefinder circuit is configured to control the dividing factor in... | 10/21/2008 |
| 7435942 | Signal processing method for optical sensors A signal processing method is provided for sensing movement of an optical sensor relative to a surface. Generally, the method includes steps of: (i) generating sets of signals responsive to motion along each of a first, second, and third direction, the directions no... | 10/14/2008 |
| 7430140 | Method and device for improved data valid window in response to temperature variation A memory architecture and a method of operating the same can provide a substantially constant data valid window (DVW) irrespective of a temperature for the memory device. Generally, a memory device can receive an access request, determine a temperature of the memory... | 09/30/2008 |
| 7428678 | Scan testing of integrated circuits with high-speed serial interface In one embodiment, an integrated circuit includes a serial link interface configured to send and receive data over a serial bus both during normal operation and during scan tests. The integrated circuit may include data routing circuitry for transferring data betwee... | 09/23/2008 |
| 7427742 | Microlens for use with a solid-state image sensor and a non-telecentric taking lens An imager includes a two-dimensional array of photosensors, each photosensor having a center point. A non-telecentric lens is positioned over the two-dimensional array of photosensors, and a two-dimensional array of microlenses is positioned over the two-dimensional... | 09/23/2008 |
| 7426142 | Device and method for sensing programming status of non-volatile memory elements A test circuit can test a status of a group of non-volatile elements. A current flowing to the group of non-volatile elements can be compared against a reference value. If the current is determined to be outside of a predetermined range, the non-volatile elements ca... | 09/16/2008 |
| 7425489 | Self-aligned shallow trench isolation A method of making a semiconductor structure includes etching an isolation oxide. The isolation oxide is in a substrate, a gate layer is on the substrate, a patterned metallic layer is on the gate layer, and a first patterned etch-stop layer is on the metallic layer... | 09/16/2008 |
| 7424650 | Circuit to measure skew A method and test circuits for measuring skew between two circuit blocks of an integrated circuit. A first data signal is propagated through a first circuit block and a first clock signal is propagated through a second circuit block. The first data signal is latched... | 09/09/2008 |
| 7421559 | Apparatus and method for a synchronous multi-port memory A synchronous multi-port memory including a plurality of ports coupled with a memory array, each of the plurality of ports including a delay stage to delay a memory access while a memory access arbitration is performed. The synchronous multi-port memory may also inc... | 09/02/2008 |
| 7420975 | Method and apparatus for a high-speed frame tagger In one embodiment, the invention is an apparatus. The apparatus includes a network processor interface suitable for coupling to a network processor. The apparatus further includes a central processor interface suitable for coupling to a central processor. The appara... | 09/02/2008 |
| 7417485 | Differential energy difference integrator Embodiments of the invention are generally directed to a high-speed differential energy difference integrator (EDI) for adaptive equalizers. In an embodiment, the EDI includes two differential full-wave rectifiers providing differential outputs that are cross-couple... | 08/26/2008 |
| 7405683 | Extending the dynamic range in an energy measurement device An apparatus for measuring energy usage. The apparatus can include an amplifier having a plurality of gain stages and the amplifier can be for receiving an input signal. The apparatus can also include an analog-to-digital converter that is coupled to the amplifier. ... | 07/29/2008 |
| 7405474 | Low cost thermally enhanced semiconductor package In one embodiment, a device is packaged using a low-cost thermally enhanced ball grid array (LCTE-BGA) package. The device may include a die with its backside mounted to the bottom side of a multi-layer packaging substrate. Thermal vias may be formed through the sub... | 07/29/2008 |
| 7406674 | Method and apparatus for generating microcontroller configuration information A method and apparatus for configuring a microcontroller. An XML description of the microcontroller's hardware resources may be accessed. A user may select from available hardware resources and pre-defined user modules to select a configuration. Configuration inform... | 07/29/2008 |
| 7403446 | Single late-write for standard synchronous SRAMs Synchronous SRAM may conform to Std. Sync or early-write at an external interface whilst providing late-write internally. ... | 07/22/2008 |
| 7400620 | Method and apparatus for handling small packets In one embodiment, the invention is an apparatus. The apparatus includes comparison logic to compare received data values to an expected data value, producing a first result. The apparatus also includes combinatorial logic coupled to the comparison logic. The combin... | 07/15/2008 |
| 7400183 | Voltage controlled oscillator delay cell and method A delay cell circuit (200) is disclosed. The delay cell circuit may include a differential stage (202) and a cross-coupled stage (204). The cross-coupled stage can include resistors (210-0 and 210-1) the function to r... | 07/15/2008 |
| 7394716 | Bank availability indications for memory device and method therefor In one arrangement, a memory device (100) can include a number of banks (102-0 to 102-2n) and corresponding counters (104-0 to 104-2n). In response to a corresponding active access ... | 07/01/2008 |
| 7394075 | Preparation of integrated circuit device samples for observation and analysis In one embodiment, a sample of an integrated circuit device is prepared for observation in a transmission electron microscope (TEM). The sample may be placed on a surface formed by vertical edges of several TEM grids. The sample may be affixed to a vertical edge of ... | 07/01/2008 |
| 7392495 | Method and system for providing hybrid clock distribution A method and system for providing hybrid clock distribution is disclosed. The distribution architecture uses a grid distribution at the top level and a balanced buffer tree distribution at the block level. The method includes determining the block layout of an integ... | 06/24/2008 |
| 7391104 | Non-stick detection method and mechanism for array molded laminate packages An integrated circuit packaging device includes a laminate substrate. A first surface of the substrate can be mounted on an integrated circuit and the second surface can be mounted on a surface of a printed circuit board. The device can also include an array of lead... | 06/24/2008 |
| 7388350 | Battery with electronic compartment An electronic containment battery includes a battery section and an electronic section that together form a standard battery form factor that allows insertion into conventional electronic devices. The electronic section can include Radio Frequency (RF) circuitry tha... | 06/17/2008 |
| 7386740 | Method for efficient supply of power to a microcontroller A method and a system for supplying power to a microcontroller with a single cell. One embodiment of the present invention discloses incorporation of a power supply pump circuit with the microcontroller and their dynamic interaction. The microcontroller sends its po... | 06/10/2008 |
| 7385793 | Cascode active shunt gate oxide project during electrostatic discharge event A method and apparatus to provide electrostatic discharge (ESD) protection to electronic circuits using a gate clamp circuit. ... | 06/10/2008 |
| 7384833 | Stress liner for integrated circuits In one embodiment, a self-aligned contact (SAC) trench structure is formed through a dielectric layer to expose an active region of a MOS transistor. The SAC trench structure not only exposes the active region for electrical connection but also removes portions of a... | 06/10/2008 |
| 7382805 | Method and apparatus for aggregating Ethernet streams Embodiments of a method and apparatus for aggregating Ethernet streams are generally described. According to but one example embodiment, implementations of a physical coding sublayer (PCS) modify one or more Ethernet streams to uniquely distinguish at least one of t... | 06/03/2008 |
| 7383370 | Arbiter circuit and signal arbitration method An arbiter circuit (100) can include a latch circuit (102) that latches competing input signals (MATCH1 and MATCH2) to generate signals on latch output (110-0 and 110-1). A filter section (104) can preve... | 06/03/2008 |
| 7379860 | Method for integrating event-related information and trace information A method for emulating and debugging a microcontroller. In one embodiment, an event thread is executed on an emulator that operates in lock-step with the microcontroller. Event information is sampled at selected points. Trace information is also recorded at the sele... | 05/27/2008 |
| 7379467 | Scheduling store-forwarding of back-to-back multi-channel packet fragments Disclosed is an apparatus and method for an interface for scheduling the store-forwarding of back-to-back multi-channel packet fragments. The apparatus may include a data extraction block, a plurality of data assemblers, a scheduler, and an output memory. The schedu... | 05/27/2008 |
| 7375535 | Scan method and topology for capacitive sensing A capacitive sensing system (100) can connect groups of capacitive sensors (112-1 to 112-N) to a common node (106) to detect change in capacitance. States of a set of capacitive sensors (112-1 to 112-N) can thu... | 05/20/2008 |
| 7371637 | Oxide-nitride stack gate dielectric A method of making a semiconductor structure comprises forming an oxide layer on a substrate; forming a silicon nitride layer on the oxide layer; annealing the layers in NO; and annealing the layers in ammonia. The equivalent oxide thickness of the oxide layer and t... | 05/13/2008 |
| 7372321 | Robust start-up circuit and method for on-chip self-biased voltage and/or current reference A reference circuit can include a reference section that provides a reference value for other circuits of an integrated circuit and can be enabled and disabled in response to an enable signal. The reference circuit can include at least a first node, draw a reference... | 05/13/2008 |
| 7372928 | Method and system of cycle slip framing in a deserializer A method and system for cycle slip framing is disclosed. The method includes receiving an asynchronous signal and generating a synchronous pulse after receiving the asynchronous signal. The method further provides that the synchronous pulse be used to affect a bit s... | 05/13/2008 |
| 7368770 | Well region with rounded corners A semiconductor imager structure having a well region formed in a substrate layer. The well region being of a predetermined shape having a plurality of corners being non-right angles. ... | 05/06/2008 |
| 7365569 | High-speed level shifter Embodiments of a high-speed level shifter are described. The level shifter may include a first transistor having a drain, a source, and a gate and a second transistor having a drain, a source, and a gate. The first and second transistors may be operable to receive a... | 04/29/2008 |
| 7362079 | Voltage regulator circuit A voltage regulator circuit has a standby amplifier with an output coupled to a gate of an output transistor. An active amplifier has an output coupled to the gate of the output transistor and to a gate of a replica follower transistor. A voltage regulated output is... | 04/22/2008 |
