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A fork with timer for providing a cue to a user after an elapsed period of time for indicating that another bite of food using the fork may be taken.
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| Number | Title | Issue Date |
| 6326853 | Circuitry, architecture and method(s) for phase matching and/or reducing load capacitance, current and/or power consumption in an oscillator An apparatus comprising a first circuit and a second circuit. The first circuit may be configured to generate a plurality of clock signals each in response to (i) one or more control inputs and (ii) one or more of a plurality of phase timing elements. The... | 12/04/2001 |
| 6249825 | Universal serial bus interface system and method A system for reconfiguring a peripheral device having a first configuration connected by a computer bus and a port to a host computer. The system comprises a first circuit and a second circuit. The first circuit may be configured to download information f... | 06/19/2001 |
| 6201407 | Circular product term allocations scheme for a programmable device A circular product term allocator configured to provide connections for product term signals to macrocells of a programmable logic device is provided. The circular product term allocator may provide such connections through a logic OR function. Alternativ... | 03/13/2001 |
| 6167528 | Programmably timed storage element for integrated circuit input/output A programmable skew buffer for optimizing the timing at the input or output pins of a memory device. The timing at each input and output pin of the memory device can be adjusted on an independent basis by coupling each input or output pin to a separate pr... | 12/26/2000 |
| 5907784 | Method of making multi-layer gate structure with different stoichiometry silicide layers A method of forming a multi-layer silicide gate structure for a MOS type semiconductor device that includes the processing steps of first providing a substrate, then depositing a gate oxide layer on the substrate, then depositing a first refractory metal ... | 05/25/1999 |
| 5907255 | Dynamic voltage reference which compensates for process variations A dynamic voltage reference circuit for generating one or more control signals for use in controlling a delay circuit or other circuit that requires compensation for process variations. The control signals are generated without drawing DC current at times... | 05/25/1999 |
| 5684434 | Erasable and programmable single chip clock generator A programmable circuit for generating a clock signal is disclosed. The present invention provides a clock generator architecture that combines PLL-based clock generator circuitry with an on-chip EPROM in a monolithic clock generator chip. The clock genera... | 11/04/1997 |
| 5666310 | High-speed sense amplifier having variable current level trip point An improved high-speed sense amplifier is disclosed for use in programmable logic devices (PLDs) and complex PLDs. The sense amplifier includes a transresistance amplifier portion that provides a voltage potential to a first node of a memory array, which ... | 09/09/1997 |
| 5648669 | High speed flash memory cell structure and method A fast, fieldless flash memory cell includes an erase node having a control gate and a floating gate, both formed of polycrystalline silicon, a program transistor sharing the floating gate and control gate with the erase node, and a read transistor sharin... | 07/15/1997 |
| 5559447 | Output buffer with variable output impedance An output buffer with a variable output impedance is described. The buffer is designed so that the output impedance is set relatively low during the initial portion of the output transition in which the step would occur. The output impedance is increased ... | 09/24/1996 |
| 4963769 | Circuit for selective power-down of unused circuitry A power reduction circuit for selectively providing power to circuitry associated with and coupled to the power reduction circuit, which includes two transistors having current paths coupled in parallel and a nonvolatile programmable storage device having... | 10/16/1990 |
| 4933899 | Bi-CMOS semiconductor memory cell A Bi-CMOS ECL semiconductor memory cell having a read word line, a write word line and a read bit line is disclosed. The cell includes a bistable circuit having complimentary outputs and also includes a first transfer device and a second transfer device, ... | 06/12/1990 |
| 4918664 | Apparatus and method for preserving data integrity in multiple-port RAMS The invention relates to a random access memory having more than one port capable of accessing the same storage addresses. It provides a system for protection of data integrity at each port. First and second ports are capable of providing first and second... | 04/17/1990 |
| 4877978 | Output buffer tri-state noise reduction circuit The invention pertains to an output buffer circuit capable of switching from the off state to the on state, and from the on state to the off state, without generating significant noise. The circuit includes an MOS inverter circuit having a first node adap... | 10/31/1989 |
