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| Number | Title | Issue Date |
| 7810005 | Method and system for correcting timing errors in high data rate automated test equipment A system and method for reducing timing errors in automated test equipment (ATE) offering increased data rates for the testing of higher-speed integrated circuits. Embodiments provide an effective mechanism for increasing the data rate of an ATE system by delegating... | 10/05/2010 |
| 7805628 | High resolution clock signal generator A clock signal generator having first and second coarse delay circuits connected in series delays pulses of a reference signal having period Tp to produce pulses of the clock signal. The first coarse delay circuit delays pulses of the reference signal wit... | 09/28/2010 |
| 7765443 | Test systems and methods for integrated circuit devices One embodiment of the invention is a portion of a test system that includes a timing generation circuit and a formatter that are coupled together, which are on a single CMOS (complementary metal oxide semiconductor) integrated circuit. The timing Generation circuit ... | 07/27/2010 |
| 7761751 | Test and diagnosis of semiconductors A method and system for performing diagnosing in an automatic test environment. The method begins by determining a fail condition during a test of a device under test (DUT). A diagnostic suite is determined for testing the fail condition. The diagnostic suite is gen... | 07/20/2010 |
| 7627790 | Apparatus for jitter testing an IC An integrated circuit tester channel includes an integrated circuit (IC) for adding a programmably controlled amount of jitter to a digital test signal to produce a DUT input signal having a precisely controlled jitter pattern. The IC also measures periods between s... | 12/01/2009 |
| 7615990 | Loadboard enhancements for automated test equipment An enhanced loadboard and method for enhanced automated test equipment (ATE) signaling. More specifically, embodiments provide an effective mechanism for reducing signal degradation and error interjection by replacing one or more relays with signal splitters for dir... | 11/10/2009 |
| 7532014 | LRL vector calibration to the end of the probe needles for non-standard probe cards for ATE RF testers A method and apparatus for radio frequency vector calibration of s-parameter measurements to the tips of the wafer probe needles of an automatic test equipment production tester. The method involves a modified Line-Reflect-Line (LRL) calibration routine that uses a ... | 05/12/2009 |
| 7496467 | Automatic test equipment operating architecture An integrated circuit testing device, such as an ATE, configured with an architecture comprising a distinct software layer and a distinct hardware layer with an interface for tester abstraction providing a communication conduit between the software layer and the har... | 02/24/2009 |
| 7492181 | Method and device for enabling the measurement of device under test voltages using a testing instrument of limited range A method for determining an output voltage of a device under test is disclosed. In the method, a first voltage is placed onto a terminal of a resister that is coupled to the device under test and a first current is through the resistor that corresponds to the first ... | 02/17/2009 |
| 7471753 | Serializer clock synthesizer A clock synthesizer uses a serializer to convert a parallel data stream into clock signals. The frequency of the synthesized clock is dependent on the bit values of the parallel data stream and the frequency of the reference clock used by the serializer. Rapid tunin... | 12/30/2008 |
| 7471100 | Semiconductor integrated circuit tester with interchangeable tester module A test head for an integrated circuit tester includes a main chassis defining a chamber that is open at the top. Tester modules are installed in the chamber, each tester module being removable as a unit from the chamber and including a tester module chassis, multipl... | 12/30/2008 |
| 7454678 | Scan stream sequencing for testing integrated circuits A system and method for processing scan data for integrated circuit testing. Scan data is divided into three groups of scan data segments: scan-in data segments, scan-out data segments and scan-mask data segments. The sequence of scan data segments in each group con... | 11/18/2008 |
| 7439728 | System and method for test socket calibration using composite waveform A system and method for calibration of a test socket using a composite waveform. A group of input signal pins of test system are coupled together. A pin belonging to the group is selected as a pin under calibration. A first calibration edge is applied to the pin und... | 10/21/2008 |
| 7430130 | D-optimized switching converter A switching converter produces an output signal transmitted to a variable load impedance to produce a load voltage VDD across the load impedance and holds VDD close to a set point voltage VSP selected by control data DREF1 | 09/30/2008 |
| 7414438 | Clock based voltage deviation detector The clock based voltage deviation detector of the present invention includes a pulse module, an indicator module and a correlation module. The pulse module generates a stream of reset pulses as a function of a clock signal. The indicator module generates a pass/fail... | 08/19/2008 |
| 7409617 | System for measuring characteristics of a digital signal An electronic device under test (DUT) responds to a digital input signal by generating a digital DUT output signal conveying a repetitive digital signal pattern. An apparatus for measuring various characteristics of the DUT output signal includes a trigger generator... | 08/05/2008 |
| 7400154 | Apparatus and method for detecting photon emissions from transistors A system, apparatus, and method for analyzing photon emission data to discriminate between photons emitted by transistors and photons emitted by background sources. The analysis involves spatial and/or temporal correlation of photon emissions. After correlation, the... | 07/15/2008 |
| 7389449 | Edge selecting triggering circuit A triggering circuit asserts a trigger signal in response to edges of a digital signal conveying a repetitive pattern of edges. The triggering circuit generates first data having a value identifying a position within the pattern of a last occurring edge of the digit... | 06/17/2008 |
| 7372302 | High speed, out-of-band differential pin driver A driver block for a differential pin driver that supports out-of-band signaling. The driver block includes a main enable switch that is controlled by a high speed driver inhibit (DINH) signal. The main enable switch controls coupling between a main current source a... | 05/13/2008 |
| 7370255 | Circuit testing with ring-connected test instrument modules Method and apparatus for circuit testing with ring-connected test instrument modules. A system for controlling one or more test instruments to test one or more integrated circuits includes a master clock and a controller. The test instruments are connected to form a... | 05/06/2008 |
| 7353126 | Method of determining coherent test conditions A method of determining coherent test conditions is disclosed. The method includes receiving constraints from a user, wherein the constraints include desired test conditions, desired tolerances for the desired test conditions, and desired instrument. Further, the me... | 04/01/2008 |
| 7343538 | Programmable multi-function module for automatic test equipment systems A programmable source/measurement module for automatic test equipment is disclosed. A high resolution low frequency source, high resolution low frequency measurement capability, low resolution high frequency source, and a low resolution high frequency measurement ca... | 03/11/2008 |
| 7336066 | Reduced pin count test method and apparatus Testing of an electronic device is carried out by combining power and signal delivery on a single pair of wires. The power delivery is decoupled from the signal delivery, using inductors, so the device power supplied does not interfere with the test signals delivere... | 02/26/2008 |
| 7327452 | Light beam apparatus and method for orthogonal alignment of specimen A system for orthogonal alignment of a specimen disclosed. The system includes a light-beam illumination source, collection optics, imaging optics, and a tiltable specimen holder. The light-beam source is activated to illuminate a spot on the specimen, and the imagi... | 02/05/2008 |
| 7323862 | Apparatus and method for detecting photon emissions from transistors A system, apparatus, and method for analyzing photon emission data to discriminate between photons emitted by transistors and photons emitted by background sources. The analysis involves spatial and/or temporal correlation of photon emissions. After correlation, the... | 01/29/2008 |
| 7314767 | Method for local wafer thinning and reinforcement A method is provided for preparing a semiconductor wafer for testing. The method includes selecting a die to be tested; measuring a diagonal of the die; thinning an area over the die extending beyond the scribe lines, the thinned area may be a circular area having a... | 01/01/2008 |
| 7307440 | Semiconductor integrated circuit tester with interchangeable tester module A test head for an integrated circuit tester includes a main chassis defining a chamber that is open at the top. Tester modules are installed in the chamber, each tester module being removable as a unit from the chamber and including a tester module chassis, multipl... | 12/11/2007 |
| 7297948 | Column simultaneously focusing a particle beam and an optical beam The invention concerns a column for producing a focused particle beam comprising: a device (100) focusing particles including an output electrode (130) with an output hole (131) for allowing through a particle beam (A); an optical focusing devic... | 11/20/2007 |
| 7296195 | Bit synchronization for high-speed serial device testing An apparatus for testing electronic devices employs a programmable device to adjust the timing of the strobes such that the strobes sample the bit stream from a device under test at or near the center of the bit position. The strobe time adjustment is performed base... | 11/13/2007 |
| 7292059 | Power supply assembly for a semiconductor circuit tester A power supply assembly includes a dielectric substrate and a power supply circuit supported by the dielectric substrate. A conductive connection block is attached to the dielectric substrate at a main surface thereof and is connected to a power supply terminal of t... | 11/06/2007 |
| 7271664 | Phase locked loop circuit A phase locked loop circuit (PLL) has a reference terminal for receiving a reference signal and an output terminal for providing an output signal. The PLL comprises a phase comparator having first and second inputs and having an output at which it provides a signal ... | 09/18/2007 |
| 7257507 | System and method for determining probing locations on IC An apparatus and method for tracing back a probing location to identify the circuit element being probed on a device under test (DUT). The coordinates of the irregularity on the DUT are used to trace back to the logic cone to decipher the root-cause of the irregular... | 08/14/2007 |
| 7254203 | Method and apparatus for use of high sampling frequency A/D converters for low frequency sampling A method and apparatus for adding fill-in clock pulses to an analog to digital converters input clock signal between requests for analog data acquisition. The circuit that provides the fill-in clock pulses is able to detect a request for analog data acquisition, syn... | 08/07/2007 |
| 7246026 | Multi-domain execution of tests on electronic devices A device under test is divided into multiple test domains, and test conditions for each of the multiple test domains are defined separately, so that each test domain has its own test pattern, timing data, and other test conditions. Each test domain can start and sto... | 07/17/2007 |
| 7245133 | Integration of photon emission microscope and focused ion beam An integrated FIB/PEM apparatus and method for performing failure analysis on integrated circuits. In-situ failure analysis is enabled by integrating Photon Emission Microscopy into a Focused Ion Beam system, thereby improving throughput and efficiency of Failure An... | 07/17/2007 |
| 7243278 | Integrated circuit tester with software-scaleable channels An integrated circuit tester for testing an IC device under test (DUT) during a succession of test cycles includes a pattern generator programmed to generate data before each test cycle encoded to specify all test activities to be carried out during the test cycle a... | 07/10/2007 |
| 7243039 | System and method for determining probing locations on IC A method for identifying an area of a chip to be probed proceeds as follows. A callout list of failures is obtained from a tester, the list including cell name and pin for each failure. A Def file is interrogated to locate a Def entry matching the cell name, and a c... | 07/10/2007 |
| 7242257 | Calibration-associated systems and methods The present invention relates to test systems for testing integrated circuit devices and to calibration associated systems and methods. One embodiment of the invention provides an auto-calibration system. The system includes: a plurality of delay line elements (DLEs... | 07/10/2007 |
| 7230240 | Enhanced scanning control of charged particle beam systems A charged particle beam system and scanning control method capable of imaging, and possibly editing, a device under test (DUT). The charged particle beam system contains a charged particle beam generation unit, such as a focused ion beam (FIB) column, which emits a ... | 06/12/2007 |
| 7228464 | PICA system timing measurement and calibration PICA probe system apparatus is described, including apparatus for calibrating an event timer having a coarse measurement capability in which time intervals defined by clock boundaries are counted and a fine measurement capability in which time between boundaries is ... | 06/05/2007 |
