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Neuroimaging as a Marketing Tool
Neuroimaging as a means for validating whether a stimulus such as advertisement, communication, or product evokes a certain mental response such as emotion, preference, or memory, or to predict the consequences of the stimulus on later behavior such as consumption or purchasing.
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| Number | Title | Issue Date |
| 6173428 | Apparatus and method for testing using clocked test access port controller for level sensitive scan designs A test access port controller for use in a level sensitive scan design having test design logic including at least one serial scan test path. The test access port controller includes test access port controller logic operable in a system test mode for con... | 01/09/2001 |
| 6128639 | Array address and loop alignment calculations Division system and method support a hardware division address centrifuge to provide a flexible addressing scheme, and thus facilitates the reorganization and redistribution of data between remote and local memory blocks in a distributed memory massively ... | 10/03/2000 |
| 6116915 | Stop align lateral module to module interconnect An information handling system includes stacks of printed circuit boards interconnected using an interconnection system. The printed circuit boards include network boards, system interface boards, memory boards, and central processing unit boards. The int... | 09/12/2000 |
| 6119198 | Recursive address centrifuge for distributed memory massively parallel processing systems A method for extracting a PE number and offset from an array index by recursive centrifuging. According to one aspect of the present invention, a processing element number is assigned to each processing element, a local memory address is assigned to each ... | 09/12/2000 |
| 6101181 | Virtual channel assignment in large torus systems A multiprocessor computer system includes processing element nodes interconnected by physical communication links. Routers route messages between processing element nodes on the physical communication links. Each router includes input ports for receiving ... | 08/08/2000 |
| 6098162 | Vector shift functional unit for successively shifting operands stored in a vector register by corresponding shift counts stored in another vector register Vector shifting elements of a vector register by varying amounts in a single process is achieved in a vector supercomputer processor. A first vector register contains a set of operands, and a second vector register contains a set of shift counts, one shif... | 08/01/2000 |
| 6092226 | Fabrication of test logic for level sensitive scan on a circuit An input cell to the core logic on an electrical component and an output cell from the core logic on an electrical component are provided with a first signal path for data, a second signal path for scan data, a flip flop positioned near the pad of the cor... | 07/18/2000 |
| 6085303 | Seralized race-free virtual barrier network Improved method and apparatus for facilitating barrier and eureka synchronization in a massively parallel processing system. The present barrier/eureka synchronization mechanism provides a partitionable, low-latency, immediately reusable, robust mechanism... | 07/04/2000 |
| 6055618 | Virtual maintenance network in multiprocessing system having a non-flow controlled virtual maintenance channel A multiprocessor computer system includes processing element nodes interconnected with physical communication links in an n-dimensional topology. A flow controlled virtual channel has virtual channel buffers assigned to each physical communication link to... | 04/25/2000 |
| 6055157 | Large area, multi-device heat pipe for stacked MCM-based systems The invention is a computer module for scalably adding computing power and cooling capacity to a computer system. Computing power can be added by merely adding additional printed circuit cards to the computing module. Cooling capability is added by adding... | 04/25/2000 |
| 6029212 | Method of handling arbitrary size message queues in which a message is written into an aligned block of external registers within a plurality of external registers A system and method of accessing a memory location within a system having a processor and a plurality of memory locations separate from the processor. The system includes a plurality of external registers which are connected to the processor over a data b... | 02/22/2000 |
| 6018459 | Porous metal heat sink A heat sink is disclosed having an elongate, porous metal structure, including multiple sets of thermally conductive members. The members, which are interwoven, direct heat away from a heat producing component. The elongate structure of the matrix structu... | 01/25/2000 |
| 6012135 | Computer having multiple address ports, each having logical address translation with base and limit memory management Method and apparatus for a logical address translator which translates a logical address into a physical address in a computer. The computer includes a plurality of address ports. Each address port includes a logical address translator, which includes a p... | 01/04/2000 |
| 5987626 | Precise detection of errors using hardware watchpoint mechanism The precise detection of errors in computer programs using the hardware watchpoint mechanism found in computers is disclosed. In one embodiment, a software detection phase of a method detects the approximate location of an error, generating information re... | 11/16/1999 |
| 5970232 | Router table lookup mechanism A multiprocessor computer system includes processing element nodes interconnected by physical communication links in a n-dimensional topology, which includes at least two global partitions. Routers route messages between processing element nodes and inclu... | 10/19/1999 |
| 5963428 | Cooling cap method and apparatus for tab packaged integrated circuit The present invention discloses a method and apparatus for bridging the gap between an integrated circuit package or component mounted on a circuit board and a heat sink such that there is little stress placed on the component, but there is still a connec... | 10/05/1999 |
| 5960081 | Embedding a digital signature in a video sequence Method and apparatus for watermarking digital video material by embedding a digital signature. One embodiment of the system integrates the embedding procedure into a block-based compression scheme. In one embodiment, a 32-bit digital signature is embedded... | 09/28/1999 |
| 5958017 | Adaptive congestion control mechanism for modular computer networks A congestion control mechanism for a node of a modular computer network system. The mechanism includes registers for maintaining the number of undelivered requests and unanswered requests for the node and registers for the maximum number of such undeliver... | 09/28/1999 |
| 5946496 | Distributed vector architecture A vector/scalar computer system has nodes interconnected by an interconnect network. Each node includes a vector execution unit, a scalar execution unit, physical vector registers holding physical vector elements, a mapping vector register holding a mappi... | 08/31/1999 |
| 5940625 | Density dependent vector mask operation control apparatus and method A vector processing system which uses vector masks to determine whether or not to perform operations on operands corresponding to bit positions within the mask is disclosed. An approximation of the number of no-operation representative bits in a vector ma... | 08/17/1999 |
| 5920714 | System and method for distributed multiprocessor communications In a tightly coupled communication scheme based on a common shared resource circuit having a plurality of shared information registers and adapted particularly to a multiprocessing system having 2N CPUs, a method of performing a read-and-modify... | 07/06/1999 |
| 5913069 | Interleaving memory in distributed vector architecture multiprocessor system A vector/scalar computer system has nodes interconnected by an interconnect network. Each node includes a vector execution unit, a scalar execution unit, physical vector registers, and a memory. The physical vector registers from the nodes together form a... | 06/15/1999 |
| 5900023 | Method and apparatus for removing power-of-two restrictions on distributed addressing An efficient integer-division-by-an-constant method and apparatus. This integer-division-by-an-constant is useful in calculations which must be performed often and/or quickly, and where the denominator is fixed for the calculations, such as address calcul... | 05/04/1999 |
| 5895501 | Virtual memory system for vector based computer systems A virtual memory management system for a vector based processing system detects early page or segment faults allowing pipelined instructions to be halted and resumed once the pages or segments required for a job are available in main storage. A multiplier... | 04/20/1999 |
| 5864738 | Massively parallel processing system using two data paths: one connecting router circuit to the interconnect network and the other connecting router circuit to I/O controller A system and method of transferring information between a peripheral device and an MPP system having an interconnect network and a plurality of processing nodes. Each processing element includes a processor, local memory and a router circuit connected to ... | 01/26/1999 |
| 5862313 | Raid system using I/O buffer segment to temporary store striped and parity data and connecting all disk drives via a single time multiplexed network A system and method for implementing a serial RAID system. Data is striped for the array of disk drives and parity for the striped data is calculated and the resulting data and is written serially to a RAID system over a Fibre Channel or other type of net... | 01/19/1999 |
| 5848286 | Vector word shift by vo shift count in vector supercomputer processor Vector shifting elements of a vector register by varying amounts in a single process is achieved in a vector supercomputer processor. A first vector register contains a set of operands, and a second vector register contains a set of shift counts, one shif... | 12/08/1998 |
| 5841973 | Messaging in distributed memory multiprocessing system having shell circuitry for atomic control of message storage queue's tail pointer structure in local memory A messaging facility in a multiprocessor computer system includes assembly circuitry in a source processing element for assembling a message to be sent from the source processing element to a destination processing element based on information provided fr... | 11/24/1998 |
| 5835925 | Using external registers to extend memory reference capabilities of a microprocessor A system and method of accessing a memory location within a system having a processor and a plurality of memory locations separate from the processor. The system includes a plurality of external registers which are connected to the processor over a data b... | 11/10/1998 |
| 5805788 | Raid-5 parity generation and data reconstruction A system for implementing RAID-5 parity generation and reconstruction. Data for an array of disk drives is placed in an I/O buffer. The RAID-5 parity engine creates parity data and stores the resulting parity data in the I/O buffer as well. The I/O buffer... | 09/08/1998 |
| 5805418 | Cooling cap method and apparatus for tab packaged integrated circuits The present invention discloses a method and apparatus for bridging the gap between an integrated circuit package or component mounted on a circuit board and a heat sink such that there is little stress placed on the component, but there is still a connec... | 09/08/1998 |
| 5802341 | Method for the dynamic allocation of page sizes in virtual memory A system and method for virtual memory management. A plurality of virtual memory pages having selectable page sizes are used to tailor memory allocations in a way which balances overallocation of memory against the number of entries saved in accessing tha... | 09/01/1998 |
| 5801924 | Method and apparatus for cooling daughter card modules A method and apparatus for conductively cooling daughter card assemblies mounted to either an air or liquid cooled computer circuit module wherein the module has a cold plate and at least one mother board adjacent the cold plate. The module carries a numb... | 09/01/1998 |
| 5802375 | Outer loop vectorization A system and method for vectorizing a non-innermost loop of a nested loop. Iterative loops of a nested loop are analyzed to determine if they can be vectorized (vector legality). If more than one iterative loop can be vectorized, a selection criteria is a... | 09/01/1998 |
| 5784706 | Virtual to logical to physical address translation for distributed memory massively parallel processing systems Address translation means for distributed memory massively parallel processing (MPP) systems include means for defining virtual addresses for processing elements (PE's) and memory relative to a partition of PE's under program control, means for defining l... | 07/21/1998 |
| 5768104 | Cooling approach for high power integrated circuits mounted on printed circuit boards A method and apparatus for cooling high power integrated circuits mounted on a printed circuit board. The invention includes producing a cold plate adapted to receive the printed circuit board thereon. A series of thermal shims are produced in incremental... | 06/16/1998 |
| 5765181 | System and method of addressing distributed memory within a massively parallel processing system A system and address method for extracting a PE number and offset from an array index. According to one aspect of the present invention, a processing element number is assigned to each processing element, a local memory address is assigned to each memory ... | 06/09/1998 |
| 5765198 | Transparent relocation of real memory addresses in the main memory of a data processor An operating system (OS) of a data processor physically relocates segments of memory containing real addresses used by the operating system itself, which addresses must remain unaltered within the system. The system identifies a memory bank containing a s... | 06/09/1998 |
| 5761706 | Stream buffers for high-performance computer memory system Method and apparatus for a filtered stream buffer coupled to a memory and a processor, and operating to prefetch data from the memory. The filtered stream buffer includes a cache block storage area and a filter controller. The filter controller determines... | 06/02/1998 |
| 5761043 | Daughter card assembly A daughter card assembly which provides relatively high conductive heat transfer from the electronic components on the daughter board to either an air or liquid cooled cold plate of a computer circuit module. The daughter card assembly has a daughter boar... | 06/02/1998 |
