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| Number | Title | Issue Date |
| 8095759 | Error management firewall in a multiprocessor computer A multiprocessor computer system comprises a plurality of processors and a plurality of nodes, each node comprising one or more processors. A local memory in each of the plurality of nodes is coupled to the processors in each node, and a hardware firewall comprising... | 01/10/2012 |
| 8081459 | Air conditioning systems for computer systems and associated methods Computer systems with air cooling systems and associated methods are disclosed herein. In several embodiments, a computer system can include a computer cabinet holding multiple computer modules, and an air mover positioned in the computer cabinet. The computer syste... | 12/20/2011 |
| 8065573 | Method and apparatus for tracking, reporting and correcting single-bit memory errors Various embodiments include an apparatus comprising a memory device including a plurality of addressable memory locations, and a memory manager coupled to the memory device, the memory manager including a scheduling unit and a histogram data structure including a pl... | 11/22/2011 |
| 8051338 | Inter-asic data transport using link control block manager An apparatus includes a SerDes circuit and a link control block (LCB). The SerDes circuit is a first end of a SerDes circuit pair of a SerDes lane. A SerDes lane includes the SerDes circuit pair coupled by a communications medium. The LCB includes an error tracking ... | 11/01/2011 |
| 8024638 | Apparatus and method for memory read-refresh, scrubbing and variable-rate refresh A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows bein... | 09/20/2011 |
| 7984453 | Event notifications relating to system failures in scalable systems An availability system is provided that includes a hierarchy of controllers for providing event notifications relating to availability of components of a scalable MPP system. A controller receives a subscription from a child controller that identifies an event type ... | 07/19/2011 |
| 7974052 | Method and apparatus for switched electrostatic discharge protection One embodiment includes an integrated circuit including an input circuit, a first diode including a first anode and a first cathode, with the first cathode coupled to a first voltage, the first anode coupled to the input circuit at a node via a first mechanical swit... | 07/05/2011 |
| 7957412 | Lonely pulse compensation An apparatus comprising a transmission line, a receiver circuit, and a high pass filter circuit coupled between the transmission line and a receiver circuit input. The receiver circuit is configured to receive a data signal over the transmission line at a first data... | 06/07/2011 |
| 7904685 | Synchronization techniques in a multithreaded environment Various techniques for manipulating data using access states of memory, access control fields of pointers and operations, and exception raising and exception trapping in a multithreaded computer system. In particular, the techniques include synchronization support f... | 03/08/2011 |
| 7903403 | Airflow intake systems and associated methods for use with computer cabinets Airflow intake systems for use with computer cabinet air conditioning systems are disclosed herein. In one embodiment, a computer system includes a plurality of computer modules and an associated air mover positioned in an interior portion of a computer cabinet. The... | 03/08/2011 |
| 7898799 | Airflow management apparatus for computer cabinets and associated methods Airflow management apparatuses for computer cabinets and associated methods are disclosed herein. The computer cabinets include a plurality of computer modules positioned between an air inlet and an air outlet and an air mover configured to move a flow of cooling ai... | 03/01/2011 |
| 7890673 | System and method for accessing non processor-addressable memory A system and method for addressing memory and transferring data, which in some embodiments include one or more processor translation look-aside buffers (TLBs) and optionally one or more I/O TLBs, and/or a block transfer engine (BTE) that optionally includes a serial... | 02/15/2011 |
| 7852836 | Reduced arbitration routing system and method A system and method for routing packets from one node to another node in a system having a plurality of nodes connected by a network. A node router is provided in each node, wherein the node router includes a plurality of network ports, including a first and a secon... | 12/14/2010 |
| 7843929 | Flexible routing tables for a high-radix router A system and method for routing in a high-radix network. A packet is received and examined to determine if the packet can be routed adaptively. If the packet can be routed adaptively, the packet is routed adaptively, wherein routing adaptively includes selecting a c... | 11/30/2010 |
| 7830905 | Speculative forwarding in a high-radix router A system and method for speculative forwarding of packets received by a router, wherein each packet includes phits and wherein one or more phits include a cyclic redundancy code (CRC). A packet is received and phits of the packet are forwarded to router logic. A cyc... | 11/09/2010 |
| 7826996 | Memory-daughter-card-testing apparatus and method A memory daughter card (MDC) is described, having a very high-speed serial interface and an on-card MDC test engine that allows one MDC to be directly connected to another MDC for testing purposes. In some embodiments, a control interface allows the test engine to b... | 11/02/2010 |
| 7793073 | Method and apparatus for indirectly addressed vector load-add-store across multi-processors A method and apparatus to correctly compute a vector-gather, vector-operate (e.g., vector add), and vector-scatter sequence, particularly when elements of the vector may be redundantly presented, as with indirectly addressed vector operations. For an add operation, ... | 09/07/2010 |
| 7764629 | Identifying connected components of a graph in parallel A method and system for finding connected components of a graph using a parallel algorithm is provided. The connected nodes system performs a search algorithm in parallel to identify subgraphs of the graph in which the nodes of the subgraph are connected. The connec... | 07/27/2010 |
| 7757497 | Method and apparatus for cooling electronic components A spray cooling system includes a spray delivery device and a cooling liquid delivered to the spray delivery device. The spray delivery device includes one or more inlet apertures and one or more corresponding outlet apertures, at least one pair of inlet aperture an... | 07/20/2010 |
| 7751519 | Phase rotator for delay locked loop based SerDes An apparatus comprising a first multiplexer circuit (MUX) to receive a plurality of clock phase signals at a corresponding plurality of MUX inputs and to output a first clock signal and a second clock signal that are out of phase with each other, a phase delay circu... | 07/06/2010 |
| 7743223 | Decoupling of write address from its associated write data in a store to a shared memory in a multiprocessor system In a computer system having a plurality of processors connected to a shared memory, a system and method of decoupling an address from write data in a store to the shared memory. A write request address is generated for a memory write, wherein the write request addre... | 06/22/2010 |
| 7739667 | Parallelism performance analysis based on execution trace information A system for conducting performance analysis for executing tasks. The analysis involves generating a variety of trace information related to performance measures, including parallelism-related information, during execution of the task. In order to generate the trace... | 06/15/2010 |
| 7735088 | Scheduling synchronization of programs running as streams on multiple processors Systems and methods start a process in an operating system. Additionally, a plurality of program units associated with the process are started. When a context shifting event occurs, each of the plurality of program units has their scheduling synchronized and their c... | 06/08/2010 |
| 7676728 | Apparatus and method for memory asynchronous atomic read-correct-write operation A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows bein... | 03/09/2010 |
| 7630198 | Multi-stage air movers for cooling computer systems and for other uses Multi-stage air movers for cooling computers and other systems are described herein. In one embodiment, a computer system includes a computer cabinet holding a plurality of computer modules. The computer cabinet includes an air inlet and an air outlet. The computer ... | 12/08/2009 |
| 7624246 | Method and system for memory allocation in a multiprocessing environment A method and system for allocating and de-allocating memory for threads of an application is provided. An allocation system provides a heap for tracking free tokens of memory that are available for allocation to threads of an application. A heap tracks collections o... | 11/24/2009 |
| 7587305 | Transistor level verilog A method includes specifying a first set of interconnected devices associated with a first leaf cell in Verilog syntax, and specifying a second set of interconnected devices associated with a second leaf cell in Verilog syntax. A connection between the first leaf ce... | 09/08/2009 |
| 7577816 | Remote translation mechanism for a multinode system The present invention provides a method of initializing shared memory in a multinode system. The method includes building a local address space in each of a plurality of nodes and exporting the local address space from each of the plurality of nodes to a Remote Tran... | 08/18/2009 |
| 7565593 | Apparatus and method for memory bit-swapping-within-address-range circuit A memory controller and method that provide a read-refresh (also called “distributed-refresh”) mode of operation, in which every row of memory is read within the refresh-rate requirements of the memory parts, with data from different columns within the rows bein... | 07/21/2009 |
| 7558910 | Detecting access to a memory location in a multithreaded environment Various techniques for manipulating data using access states of memory, access control fields of pointers and operations, and exception raising and exception trapping in a multithreaded computer system. In particular, the techniques include synchronization support f... | 07/07/2009 |
| 7558889 | Accessing a collection of data items in a multithreaded environment Various techniques for manipulating data using access states of memory, access control fields of pointers and operations, and exception raising and exception trapping in a multithreaded computer system. In particular, the techniques include synchronization support f... | 07/07/2009 |
| 7543133 | Latency tolerant distributed shared memory multiprocessor computer A computer system having low memory access latency. In one embodiment, the computer system includes a network and one or more processing nodes connected via the network, wherein each processing node includes a plurality of processors and a shared memory connected to... | 06/02/2009 |
| 7536690 | Deferred task swapping in a multithreaded environment A method and system that prepares a task for being swapped out from processor utilization that is executing on a computer with multiple processors that each support multiple streams. The task has one or more teams of threads, where each team represents threads execu... | 05/19/2009 |
| 7533460 | Method for partitioning banks of processors in large computer systems Systems and methods for operatively connecting processor banks in large computer systems are disclosed herein. In one embodiment, a computer system includes a first bank of processors, a second bank of processors spaced apart from the first bank of processors, and a... | 05/19/2009 |
| 7519771 | System and method for processing memory instructions using a forced order queue A novel system and method for processing memory instructions. One embodiment of the invention provides a method for processing a memory instruction. In this embodiment, the method includes obtaining a memory request; storing the memory request in an Initial Request ... | 04/14/2009 |
| 7478769 | Method and apparatus for cooling electronic components A spray cooling system includes a spray delivery device and a cooling liquid delivered to the spray delivery device. The spray delivery device includes one or more inlet apertures and one or more corresponding outlet apertures, at least one pair of inlet aperture an... | 01/20/2009 |
| 7437521 | Multistream processing memory-and barrier-synchronization method and apparatus A method and apparatus to provide specifiable ordering between and among vector and scalar operations within a single streaming processor (SSP) via a local synchronization (Lsync) instruction that operates within a relaxed memory consistency model. Various aspects o... | 10/14/2008 |
| 7428727 | Debugging techniques in a multithreaded environment A system for debugging targets using various techniques, some of which are particularly useful in a multithread environment. These techniques include implementing breakpoints using out-of-line instruction emulation so that an instruction replaced with a breakpoint i... | 09/23/2008 |
| 7426732 | Placing a task of a multithreaded environment in a known state A method and system that prepares a task for being swapped out from processor utilization that is executing on a computer with multiple processors that each support multiple streams. The task has one or more teams of threads, where each team represents threads execu... | 09/16/2008 |
| 7421565 | Method and apparatus for indirectly addressed vector load-add -store across multi-processors A method and apparatus to correctly compute a vector-gather, vector-operate (e.g., vector add), and vector-scatter sequence, particularly when elements of the vector may be redundantly presented, as with indirectly addressed vector operations. For an add operation, ... | 09/02/2008 |
