Did You Know...
...that to encourage use of his new invention, the shopping cart, market owner Sylvan Goldman hired fake shoppers to push the carts around his store in Oklahoma City? Seems his customers were reluctant to give up their hand-carried baskets.
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| Number | Title | Issue Date |
| 6424953 | Encrypting secrets in a file for an electronic micro-commerce system An electronic commerce system and method includes a broker computer system having a database of scrips, a vendor computer, and a consumer computer system having a wallet protected by a pass phrase. To strengthen the pass phrase, the wallet adds a nonce an... | 07/23/2002 |
| 6421537 | Method and apparatus for providing switch capability mediation in a mobile telephone system An improved home location register (HLR) that includes a switch capability mediation module for implementing switch capability mediation between different mobile switching centers (MSCs). According to the invention, when one MSC (home MSC of a receiving p... | 07/16/2002 |
| 6408394 | System and method for applying initialization power to SCSI devices A computer is provided having a SCSI subsystem and multiple SCSI devices connected to that subsystem. Those devices involve electromechanical motors which require a greater amount of current during times needed to spin-up the motor-driven devices to a ste... | 06/18/2002 |
| 6356427 | Electrostatic discharge protection clamp for high-voltage power supply or I/O with high-voltage reference An electrostatic discharge (ESD) protection technique protects a semiconductor device against electrostatic discharge events. The technique uses an ESD protection circuit that includes a two cascode-connected clamps between the protected pad and a referen... | 03/12/2002 |
| 6330528 | Method of terminating temporarily unstoppable code executing in a multi-threaded simulated operating system An operating system is simulated to run in conjunction with a native operating system, allowing processes, particularly multi-threaded processes, originally developed for the simulated operating system to be ported to the environment of the native operati... | 12/11/2001 |
| 6298425 | Computer disk management system using doublet A-B logging Updating a single block of metadata is optimized into a single I/O operation. Resilience against single block failure and system crashes with a single or less than three I/O operations is provided. The present invention method and apparatus stores two cop... | 10/02/2001 |
| 6279062 | System for reducing data transmission between coprocessors in a video compression/decompression environment by determining logical data elements of non-zero value and retrieving subset of the logical data elements In accordance with the present invention, a method and apparatus are provided for efficiently transmitting data between stages of a decompression pipeline by implementing a control store register for minimizing the amount of data that is transferred among... | 08/21/2001 |
| 6275885 | System and method for maintaining ownership of a processor bus while sending a programmed number of snoop cycles to the processor cache A computer is provided having a bus interface unit coupled between a CPU bus, a peripheral bus (i.e., PCI bus and/or graphics bus), and a memory bus. The bus interface unit includes controllers linked to the respective buses, and a plurality of queues pla... | 08/14/2001 |
| 6272580 | Apparatus and method for dynamically elevating a lower level bus master to an upper level bus master within a multi-level arbitration system A computer system, bus interface unit, and method are provided to allocate requests to a shared bus within the computer system. The bus interface unit includes an arbiter which employs a multi-level, round-robin arbitration protocol. Configuration registe... | 08/07/2001 |
| 6272651 | System and method for improving processor read latency in a system employing error checking and correction A computer is provided having a system interface unit coupled between main memory, a CPU bus, and a PCI bus and/or graphics bus. A hard drive is typically coupled to the PCI bus. The system interface unit is configured to perform a data integrity protocol... | 08/07/2001 |
| 6262823 | System for optical time domain multiplexing of digital signals In a system for communicating optically encoded data among a network of nodes, the nodes are connected to each other by optical transmit and receive fibers. Each node includes a laser, a transmitter, and a receiver connected to the transmitters of the oth... | 07/17/2001 |
| 6259435 | Obfuscated keyboard scan A keyboard input device includes a processor repeatedly executing a scan routine to detect key press events while masking the events from an external monitoring means. The keyboard input device has a number of finger-activatable keys, each connected at th... | 07/10/2001 |
| 6249756 | Hybrid flow control An improved hybrid flow control protocol for providing FIFO capacity to prevent overflow due to bytes arriving after the FIFO indicates it is not ready to receive any more bytes utilizes a combination of a high/low watermark and credit based system. In on... | 06/19/2001 |
| 6249879 | Root filesystem failover in a single system image environment A method and apparatus for transparent failover of a filesystem within a computer cluster is provided. For failover protection, a filesystem is physically connected to an active server node and a standby server node. A cluster file system provides distrib... | 06/19/2001 |
| 6249830 | Method and apparatus for distributing interrupts in a scalable symmetric multiprocessor system without changing the bus width or bus protocol A method for supporting multiple distributed interrupt controllers, designated as bus agents, in a symmetric multiprocessing system, which method includes the steps of assigning a unique identification number to each bus agent, receiving bus requests from... | 06/19/2001 |
| 6247109 | Dynamically assigning CPUs to different partitions each having an operation system instance in a shared memory space Multiple instances of operating systems execute cooperatively in a single multiprocessor computer wherein all processors and resources are electrically connected together. The single physical machine with multiple physical processors and resources is subd... | 06/12/2001 |
| 6247059 | Transaction state broadcast method using a two-stage multicast in a multiple processor cluster In a multiple processing system comprising multiple communicatively interconnected nodes, each node having one or more processor units, multicast messages sent by a sender node will contain information that allows intended receiver nodes to check and dete... | 06/12/2001 |
| 6247139 | Filesystem failover in a single system image environment A method and apparatus for transparent failover of a filesystem within a computer cluster is provided. For failover protection, a filesystem is physically connected to an active server node and a standby server node. A cluster file system provides distrib... | 06/12/2001 |
| 6230227 | Computer system with support for a subtractive agent on the secondary side of a PCI-to-PCI bridge A computer system for supporting a subtractive agent on a secondary PCI bus is provided. A bridge resides between a primary PCI bus and a secondary PCI bus. Where both a master device and a target device reside on the secondary PCI bus, the bridge employs... | 05/08/2001 |
| 6230225 | Method and apparatus for multicasting on a bus A method and apparatus for broadcasting data to multiple target devices during a single bus transaction. Each of a plurality of potential target devices detect the beginning of a primary bus transaction and retrieve transaction command and target device i... | 05/08/2001 |
| 6226755 | Apparatus and method for enhancing data transfer to or from a SDRAM system A computer system, bus interface unit employing a memory controller, and method are presented for optimizing the bandwidth data, address, and control transfer rates across a memory bus coupled to an SDRAM system. The SDRAM system is partitioned such that ... | 05/01/2001 |
| 6223271 | System and method for detecting system memory size using ROM based paging tables An apparatus and method are provided for detecting physical memory connected to a memory slot of a computer. The amount of physical memory within each bank is determined during boot up of the computer. Specifically, an extended physical address range exce... | 04/24/2001 |
| 6212587 | Device proxy agent for hiding computing devices on a computer bus A system for hiding computing devices on a computer bus comprising a computer memory for storing information pertaining to computing devices, a device proxy agent for reserving memory for storing information pertaining to hidden devices and an IOP, which ... | 04/03/2001 |
| 6208522 | Computer chassis assembly with a single center pluggable midplane board A modularized computer chassis for housing multiple computer modules, such as a processor module, media storage module, an I/O module, and power supplies includes a housing divided generally into four regions, with each region configured for receiving one... | 03/27/2001 |
| 6205500 | System and method for electrically isolating a device from higher voltage devices An isolation system and method that electrically couples a device to a bus during cycles associated with or accessing the device, but otherwise isolates the device from the bus. The isolation system includes an isolation device coupled to the device and t... | 03/20/2001 |
| 6185651 | SCSI bus extender utilizing tagged queuing in a multi-initiator environment A SCSI bus extender apparatus coupling a main SCSI bus to a auxiliary SCSI bus includes a mechanism for detecting and processing SELECTION and RESELECTION signals transmitted between the two buses to accommodate target devices on the auxiliary bus which s... | 02/06/2001 |
| 6173366 | Load and store instructions which perform unpacking and packing of data bits in separate vector and integer cache storage A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an... | 01/09/2001 |
| 6157831 | Method and apparatus for implementing configurable call forwarding bins in a mobile telephone system The present invention provides an improved home location register (HLR) that includes an application program for implementing configurable call forwarding bins in a mobile telephone system. According to the invention, a number of call forwarding bins are ... | 12/05/2000 |
| 6154816 | Low occupancy protocol for managing concurrent transactions with dependencies An architecture and coherency protocol for use in a large SMP computer system includes a hierarchical switch structure which allows for a number of multi-processor nodes to be coupled to the switch to operate at an optimum performance. Within each multi-p... | 11/28/2000 |
| 6141673 | Microprocessor modified to perform inverse discrete cosine transform operations on a one-dimensional matrix of numbers within a minimal number of instructions A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU can be coupled either through a coprocessor bus or a local central processing unit (CPU) bus to a conventional processor. The MEU employs vector regis... | 10/31/2000 |
| 6141312 | Optical tape drive that performs direct read after write operations An optical tape drive that performs direct read after write (DRAW) operations with a plurality of optical heads, each capable of reading data from and writing data to an optical tape. The optical tape drive includes control apparatus that positions each o... | 10/31/2000 |
| 6122714 | Order supporting mechanisms for use in a switch-based multi-processor system An architecture and coherency protocol for use in a large SMP computer system includes a hierarchical switch structure which allows for a number of multi-processor nodes to be coupled to the switch to operate at an optimum performance. Within each multi-p... | 09/19/2000 |
| 6111753 | Voltage regulator module A digital system that includes a main printed circuit board that has a first conductive portion formed thereon is provided. A microprocessor module is coupled to and extends orthogonally from the first conductive portion of the main circuit board. A volta... | 08/29/2000 |
| 6105146 | PCI hot spare capability for failed components A system management module (SMM) for a host server system includes a system management processor (SMP) connected to a system management local bus. The system management local bus connects to the system PCI bus through a system management central (SMC). Th... | 08/15/2000 |
| 6098134 | Lock protocol for PCI bus using an additional "superlock" signal on the system bus A computer system has a processor bus under control of the microprocessor itself, and this bus communicates with main memory, providing high-performance access for most cache fill operations. In addition, the system includes one or more expansion buses, p... | 08/01/2000 |
| 6097619 | Symmetric memory board A memory storage system includes a motherboard, a first memory card, and second memory card. The motherboard has a first and second electrical connector. The first memory card has a plurality of electrical connections coupled to the first electrical conne... | 08/01/2000 |
| 6085263 | Method and apparatus for employing commit-signals and prefetching to maintain inter-reference ordering in a high-performance I/O processor An improved I/O processor (IOP) delivers high I/O performance while maintaining inter-reference ordering among memory reference operations issued by an I/O device as specified by a consistency model in a shared memory multiprocessor system. The IOP compri... | 07/04/2000 |
| 6084499 | Planar magnetics with segregated flux paths A planar-type magnetic structure in which two coils, on two poles of the same core, are separated by an open space which is wide enough and low enough that the air return flux, through the open space, completes the flux circuit for each coil. Thus the cou... | 07/04/2000 |
| 6061794 | System and method for performing secure device communications in a peer-to-peer bus architecture A system and method for performing secure peer-to-peer device communications on an I/O bus, such as a PCI bus, a Fiber Channel bus, an IEEE, 1394 bus or a Universal Serial Bus. The system includes a plurality of intelligent I/O devices, such as intelligen... | 05/09/2000 |
| 6061521 | Computer having multimedia operations executable as two distinct sets of operations within a single instruction cycle A multimedia extension unit (MEU) is provided for performing various multimedia-type operations. The MEU may be coupled either through a coprocessor bus or a local CPU bus to a conventional processor. The MEU employs vector registers, a vector ALU, and an... | 05/09/2000 |
