Did You Know...
...that while attempting to develop a super strong glue, 3M employee Spencer Silver accidentally developed a glue that was so weak it would barely hold two pieces of paper together? However, his colleague Art Fry needed the glue. Fry sang with his church choir and marked the pages of his hymnal with small scraps of paper that often fell out. He used Silver's glue to hold the papers in place. Today we call this invention Post-it Notes.
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| Number | Title | Issue Date |
| 6553153 | Method and apparatus for reducing video data A method and apparatus for reducing video data. The apparatus is composed of a plurality of reducers. A block is received, corresponding to a plurality of color space components and having a width defined by a plurality of pixels digitally represented by ... | 04/22/2003 |
| 5802548 | Software programmable edge delay for SRAM write enable signals on dual purpose cache controllers A programmable circuit is used to modify the write enable signal used by static RAMs in cache-based personal computer systems. More specifically, the programmable circuit is used to delay or not delay the trailing edge of the cache write enable (CWE) sign... | 09/01/1998 |
| 5793385 | Address translator for a shared memory computing system An address translator for use in a system having a central processing unit, a graphics controller for generating graphics addresses which index a graphics memory address map and for feeding data to a visual display, and a system memory converts a graphics... | 08/11/1998 |
| 5781768 | Graphics controller utilizing a variable frequency clock The present invention includes a memory clock system for a graphics controller including a plurality of clock pulse generators, and a clock controller which selects the clock frequency based on the state of the graphics controller functional units.... | 07/14/1998 |
| 5638083 | System for allowing synchronous sleep mode operation within a computer A system is provided that allows for the synchronous operation of a memory controller within a computer when the local bus clock has become inactive for a predetermined period of time. The system includes a circuit that senses the presence of the local bu... | 06/10/1997 |
| 5555460 | Method and apparatus for providing a reformatted video image to a display A system which allows for the generation of grayscale video signals from color graphics images to grayscaling display devices receiving digital signals. The system is implemented advantageously in packed pixel color graphics modes of a video graphics arra... | 09/10/1996 |
| 5526025 | Method and apparatus for performing run length tagging for increased bandwidth in dynamic data repetitive memory systems A method and apparatus for improving bandwidth of sequential access to a display data memory. Display data and tag information related to consecutive data repetitions are stored. No display memory access is needed to output data to the CRT during the time... | 06/11/1996 |
| 5473572 | Power saving system for a memory controller A memory controller is provided in which the address path is disabled by a sequencer to reduce power consumption when the sequencer is in an IDLE mode. When access is requested by the bus, the sequencer changes into an ALERT mode, thereby enabling the add... | 12/05/1995 |
| 5455909 | Microprocessor with operation capture facility The present invention provides a microprocessor with a special Operation Capture Facility (OCF) mechanism which enables "faulting" whenever there is (a) a memory access request to any one of a specified plurality of blocks of memory (b) a request to acces... | 10/03/1995 |
| 5452432 | Partially resettable, segmented DMA counter A direct memory access (DMA) controller (4) utilizes a segmented counter (220). A first, byte counter portion (330) of the counter is initialized with a preselected value and decremented for each byte transfer. After the byte portion of the counter reache... | 09/19/1995 |
| 5452423 | Two-ROM multibyte microcode address selection method and apparatus An efficient organization for microcoded instruction sets which have processor operations in which not all the bits of an instruction word are required. The organization has two registers for receiving and holding the first and second byte of instructions... | 09/19/1995 |
| 5448257 | Frame buffer with matched frame rate A frame buffer architecture for a graphics controller provides for conversion of cathode ray tube (CRT) data streams to multi-segment data streams. The buffer architecture operates such that the CRT frame rate is the same as the multi-segment frame rate. ... | 09/05/1995 |
| 5432905 | Advanced asyncronous video architecture An asynchronous video system provides for the appropriate pixel data to be displayed. The system maps display control signals into a memory clock while maintaining the appropriate relationship with pixel data. Therefore, the display control signals are ge... | 07/11/1995 |
| 5422654 | Data stream converter with increased grey levels The present invention relates to An apparatus for converting cathode ray tube (CRT) to a dual panel data stream to be utilized. The present invention includes a frame buffer system for displaying data on a dual panel display, which comprises an upper and ... | 06/06/1995 |
| 5400053 | Method and apparatus for improved color to monochrome conversion A method and apparatus for improving the quality of a color-to-gray scale conversion is disclosed. A table is generated providing a visually correct conversion of all possible background/foreground colors. This table is then stored. In operation, after th... | 03/21/1995 |
| 5386584 | Interrupt-generating keyboard scanner using an image RAM A system for assisting the scanning of a keyboard associated with a personal computer. The system comprises a logic circuit which interacts with the microcontroller and the keyboard to reduce power consumption by the personal computer as well as freeing t... | 01/31/1995 |
| 5381543 | Processor system with dual clock The present invention provides a means for operating the CPU in a single chip microprocessor at a multipe of the cycle speed of the memory bus. With the present invention, first and second timing signals are provided. The frequency of the second timing si... | 01/10/1995 |
| 5327364 | Arithmetic logic unit for microprocessor with sign bit extended An arithmetic logic unit for a microprocessor is shown and described for use in a 24-bit data path where the ALU includes three separate ALU portions, one for each byte of the data path, and three separate control signals, one for each portion of the ALU.... | 07/05/1994 |
| 5325516 | Processor system with dual clock The present invention provides a means for operating the CPU in a single chip microprocessor at a multipe of the cycle speed of the memory bus. With the present invention, first and second timing signals are provided. The frequency of the second timing si... | 06/28/1994 |
| 5317694 | Fast write support for vga controller VGA controller interface circuitry that allows the VGA controller to reduce the cycle time of a write to the controller below the default write cycle time, resulting in a significant improvement of the controller's performance. The controller interface ci... | 05/31/1994 |
| 5313606 | System for detecting boundary cross-over of instruction memory space using reduced number of address bits An improved system for checking for segmentation violations counts the total number of bytes accessed from the control segment following a control transfer operation. If the count indicates that a part of an instruction is fetched from outside the control... | 05/17/1994 |
| 5305452 | Bus controller with different microprocessor and bus clocks and emulation of different microprocessor command sequences The present invention provides a system whereby the microprocessor and the bus controller in a personal computer can be driven at different frequencies. Furthermore with the present invention the COMMAND DELAY and the WAIT STATE signals on the bus can be ... | 04/19/1994 |
| 5305319 | FIFO for coupling asynchronous channels An efficient and optimized FIFO memory for use in a bus master system utilizes a multiplexing clock from which control signal defining bus cycles on asynchronous system and local buses. The FIFO facilitates interleaved access by system and local buses to ... | 04/19/1994 |
| 5297271 | Method and apparatus for performing a read-write-modify operation in a VGA compatible controller A VGA controller with a read-modify-write cycle implemented therein is provided. By implementing the read-modify-write cycle in hardware, and by reducing the data for such operations to a single address source, read-modify-write operations can be performe... | 03/22/1994 |
| 5293587 | Terminal control circuitry with display list processor that fetches instructions from a program memory, character codes from a display memory, and character segment bitmaps from a font memory Display control logic for a terminal controller with support for such features as windows and interlace. A display list processor (DLP) (20) communicates with a program memory (12) containing DLP instructions, a display memory (12) containing character co... | 03/08/1994 |
| 5285192 | Compensation method and circuitry for flat panel display A video controller for a personal computing system. The controller compensates CRT video information to generate a display compatible with a flat panel device. The controller includes registers and logic circuits which compensate CRT address information. ... | 02/08/1994 |
| 5280590 | Logic support chip for AT-type computer with improved bus architecture A support chip includes substantially all the AT core logic, namely most of the X-bus peripherals (except for the keyboard controller), memory controllers, and swapper. The normal AT data paths are altered to reduce the pin count, with a resulting surpris... | 01/18/1994 |
| 5276833 | Data cache management system with test mode using index registers and CAS disable and posted write disable A memory controller which can be used with an external tag RAM is disclosed. Existing index registers in the controller serve double duty as buffers for storing tag RAM data during a test mode. Input/output lines for the external tag RAM are coupled to th... | 01/04/1994 |
| 5276886 | Hardware semaphores in a multi-processor environment In a computer system having at least two processors, each processor having an associated memory, the processors being coupled to one another through an interface unit by means of a bus, hardware semaphores to regulate access to shared resources are disclo... | 01/04/1994 |
| 5274791 | Microprocessor with OEM mode for power management with input/output intiated selection of special address space The present invention provides a microprocessor with a special OEM mode of operation that can be used by an OEM system integrator to implement special tasks such as power management. The OEM mode provided by the present invention is designed for use by a ... | 12/28/1993 |
| 5271098 | Method and apparatus for use of expanded memory system (EMS) to access cartridge memory A method and apparatus which puts a cartridge memory, such as a cartridge ROM, into the EMS memory space. A register value is set to indicate that the cartridge memory is present. This value is provided to enable a logic circuit which does the address tra... | 12/14/1993 |
| 5247655 | Sleep mode refresh apparatus A circuit for waking a microprocessor from a sleep mode and providing it with its microprocessor clock long enough for a refresh, direct memory access (DMA) or master cycle operation to be done by external circuitry. The clock signal is then removed from ... | 09/21/1993 |
| 5245327 | Color to monochrome conversion The present invention provides a contrast enhancing method and circuit for mapping color signals into signals for driving a display which is capable of displaying shades of gray. With the present invention a preliminary translation is first made between a... | 09/14/1993 |
| 5233553 | Apparatus for performing modulo arithmetic with three-port adder A method and apparatus for emulating the intermediate 16-bit truncation of the address in the 8086 architecture using a 32-bit adder. The preferred embodiment of the invention adds the displacement, base address, and segment base values in a three-port ca... | 08/03/1993 |
| 5227989 | Arithmetic logic unit for microprocessor with sign bit extend An arithmetic logic unit for a microprocessor is shown and described for use in a 24-bit data path where the ALU includes three separate ALU portions, one for each byte of the data path, and three separate control signals, one for each portion of the ALU.... | 07/13/1993 |
| 5226047 | In-circuit emulation of a microprocessor mounted on a circuit board In-circuit emulation of a processor that is mounted on a circuit board. The processor (20) is provided with isolation circuitry wherein a particular input signal regime causes all processor outputs to be disabled. The emulator cable (60) terminates in a s... | 07/06/1993 |
| 5222212 | Fakeout method and circuitry for displays A video display controller capable of providing video control information for either a flat panel or a CRT display. The controller includes a plurality of main circuits, alternate circuits, select circuits, and a circuit for identifying the display device... | 06/22/1993 |
| 5212781 | Secondary cache control for a computer system A secondary cache control system for a computer system is disclosed. The system is utilized advantageously to reduce the cost of the SRAM while not degrading the overall performance of the CPU associated with the computer. The system latches the data from... | 05/18/1993 |
| 5210856 | Non-aligned DRAM state machine for page-mode DRAM control An apparatus and method for operating a system component in a microprocessor system. The component is operated by a component controller which runs off a clock having a frequency different than the system clock. The controller is synchronized with the sys... | 05/11/1993 |
| 5201059 | Method for reducing power consumption includes comparing variance in number of time microprocessor tried to react input in predefined period to predefined variance Two methods and apparatus for reducing power consumption in battery powered computers are disclosed. The first places the computer in a sleep mode whenever a certain data input function is called. The second applies statistical analysis to calls to anothe... | 04/06/1993 |
