Assignee: Chartered Semiconductor Manufacturing, Ltd.

Location: Singapore, SG
No. of patents: 61

Number	Title	Issue Date
8138055	Semiconductor devices having pFET with SiGe gate electrode and embedded SiGe source/drain regions and methods of making the same In a method of making a semiconductor device, a first gate stack is formed on a substrate at a pFET region, which includes a first gate electrode material. The source/drain regions of the substrate are etched at the pFET region and the first gate electrode material ...	03/20/2012
8017472	CMOS devices having stress-altering material lining the isolation trenches and methods of manufacturing thereof Semiconductor devices and methods of manufacturing thereof are disclosed. Isolation regions are formed that include a stress-altering material at least partially lining a trench formed within a workpiece. The isolation regions include an insulating material disposed...	09/13/2011
8012839	Method for fabricating a semiconductor device having an epitaxial channel and transistor having same A transistor having an epitaxial channel and a method for fabricating a semiconductor device having an epitaxial channel, the method including forming a hardmask on a substrate and forming an opening in the hardmask. The opening is geometrically characterized by a l...	09/06/2011
7960283	Method for reducing silicide defects in integrated circuits A method for forming silicide contacts in integrated circuits (ICs) is described. A spacer pull-back etch is performed during the salicidation process to reduce the stress between the spacer and source/drain silicide contact at the spacer undercut. This prevents the...	06/14/2011
7952131	Lateral junction varactor with large tuning range Large tuning range junction varactor includes first and second junction capacitors coupled in parallel between first and second varactor terminals. First and second plates of the capacitors are formed by three alternating doped regions in a substrate. The second and...	05/31/2011
7948329	Oscillator gain circuit and method A gain circuit of an oscillator circuit includes an inverter portion having an input IN and an output OUT arranged for connection to an external feedback circuit comprising a pi network. A feedback member having a first resistive element is coupled between the input...	05/24/2011
7947604	Method for corrosion prevention during planarization The present invention relates to the reduction or complete prevention of Cu corrosion during a planarization or polishing process. In one aspect of the invention, RF signal is used to establish a negative bias in front of the wafer surface following polishing to eli...	05/24/2011
7947546	Implant damage control by in-situ C doping during SiGe epitaxy for device applications Some example embodiments of the invention comprise methods for and semiconductor structures comprised of: a MOS transistor comprised of source/drain regions, a gate dielectric, a gate electrode, channel region; a carbon doped SiGe region that applies a stress on the...	05/24/2011
7939413	Embedded stressor structure and process An example embodiments are structures and methods for forming an FET with embedded stressor S/D regions (e.g., SiGe), a doped layer below the embedded S/D region adjacent to the isolation regions, and a stressor liner over reduced spacers of the FET gate. An example...	05/10/2011
7939348	E-beam inspection structure for leakage analysis A testing structure, and method of using the testing structure, where the testing structure comprised of at least one of eight test structures that exhibits a discernable defect characteristic upon voltage contrast scanning when it has at least one predetermined str...	05/10/2011
7935632	Reduced metal pipe formation in metal silicide contacts Formation of metal pipes resulting from formation of metal silicide contacts are reduced or avoided. To reduce formation of metal pipes, an epitaxial layer is formed over the diffusion region on which the metal silicide contact is formed. The epitaxial layer reduces...	05/03/2011
7935589	Enhanced stress for transistors A transistor disposed on a substrate includes a gate, spacers on gate sidewalls, and diffusion regions adjacent to the gate. Silicide contacts on the diffusion regions are displaced from the spacers by a distance G. Stressors may be provided in the diffusion region ...	05/03/2011
7932152	Method of forming a gate stack structure A method of forming an integrated circuit structure on a substrate, the substrate includes a primary region and a secondary region. A first layer of a first material of a first thickness is formed over the substrate. A portion of the first layer is removed over the ...	04/26/2011
7923365	Methods of forming field effect transistors having stress-inducing sidewall insulating spacers thereon Methods of forming integrated circuit devices include forming a field effect transistor having a gate electrode, a sacrificial spacer on a sidewall of the gate electrode and silicided source/drain regions. The sacrificial spacer is used as an implantation mask when ...	04/12/2011
7923180	Cross technology reticles A method of fabricating a device is presented. The method includes forming a mask that includes multiple images. A substrate is patterned using the mask. An image of the multiple images corresponds to a respective patterning process. The substrate is processed furth...	04/12/2011
7902066	Damascene contact structure for integrated circuits Interconnects for integrated circuits, such as damascene structures are formed using a hard mask. The hard mask is formed from, for example, high-k dielectric material such as hafnium oxide or other materials having high etch selectivity to the interconnect dielectr...	03/08/2011
7893502	Threshold voltage improvement employing fluorine implantation and adjustment oxide layer An epitaxial semiconductor layer may be formed in a first area reserved for p-type field effect transistors. An ion implantation mask layer is formed and patterned to provide an opening in the first area, while blocking at least a second area reserved for n-type fie...	02/22/2011
7846805	Self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process A structure and a process for a self-aligned vertical PNP transistor for high performance SiGe CBiCMOS process. Embodiments include SiGe CBiCMOS with high-performance SiGe NPN transistors and PNP transistors. As the PNP transistors and NPN transistors contained diff...	12/07/2010
7846800	Avoiding plasma charging in integrated circuits A circuit having a circuit control terminal, a primary circuit and a protection circuit is provided. The primary circuit includes a primary control terminal and a primary gate oxide of a thickness T1. The primary control terminal is coupled to the circuit...	12/07/2010
7863141	Integration for buried epitaxial stressor Structures and methods of fabricating isolation regions for a semiconductor device. An example method comprises the following. We form one or more buried doped regions in a substrate. We form a stressor layer over the substrate. We form a strained layer over the str...	01/04/2011
7855143	Interconnect capping layer and method of fabrication The present invention relates to an interconnect capping layer and a method of fabricating a capping layer for an interconnect. In particular, but not exclusively, the invention relates to a capping layer for a copper interconnect used to interconnect elements in an...	12/21/2010
7843673	Antenna diodes with electrical overstress (EOS) protection An antenna diode circuit for discharging static charge accumulated during wafer processing is described. The antenna diode circuit includes first and second junctions coupled to a circuit element and substrate. Between the first and second junctions is a diode circu...	11/30/2010
7838372	Methods of manufacturing semiconductor devices and structures thereof Methods of manufacturing semiconductor devices and structures thereof are disclosed. In one embodiment, a method of manufacturing a semiconductor device includes forming recesses in a first region and a second region of a workpiece. The first region of the workpiece...	11/23/2010
7833900	Interconnections for integrated circuits including reducing an overburden and annealing The present invention discloses a method of manufacturing an integrated circuit on a semiconductor substrate having a semiconductor device provided thereon, including the steps of forming a copper layer having an overburden of a desired thickness, forming a layer of...	11/16/2010
7829422	Integrated circuit having ultralow-K dielectric layer A device layer is configured to reduce change in stress characteristics due to subsequent processing to reduce cracking of a subsequently formed layer. The change in stress characteristics can be reduced by providing a shield layer over the device layer to protect t...	11/09/2010
7803704	Reliable interconnects A method for forming a semiconductor device is presented. The method includes providing a substrate prepared with a dielectric layer formed thereon. The dielectric layer having a conductive line disposed in an upper portion of the dielectric layer. The substrate is ...	09/28/2010
7800182	Semiconductor devices having pFET with SiGe gate electrode and embedded SiGe source/drain regions and methods of making the same In a method of making a semiconductor device, a first gate stack is formed on a substrate at a pFET region, which includes a first gate electrode material. The source/drain regions of the substrate are etched at the pFET region and the first gate electrode material ...	09/21/2010
7790617	Formation of metal silicide layer over copper interconnect for reliability enhancement A method of fabrication of a sputtered metal silicide layer over a copper interconnect. We form a dielectric layer over a conductive layer. We form an interconnect opening in the dielectric layer. We form a copper layer at least filling the interconnect opening. We ...	09/07/2010
7776699	Strained channel transistor structure and method A transistor device structure comprising: a substrate portion formed from a first material; and a source region, a drain region and a channel region formed in said substrate, the source and drain regions comprising a plurality of islands of a second material differe...	08/17/2010
7767577	Nested and isolated transistors with reduced impedance difference A processing layer, such as silicon, is formed on a metal silicide contact followed by a metal layer. The silicon and metal layers are annealed to increase the thickness of the metal silicide contact. By selectively increasing the thickness of silicide contacts, R	08/03/2010
7745320	Method for reducing silicide defects in integrated circuits A method for forming silicide contacts in integrated circuits (ICs) is described. A spacer pull-back etch is performed during the salicidation process to reduce the stress between the spacer and source/drain silicide contact at the spacer undercut. This prevents the...	06/29/2010
7741187	Lateral junction varactor with large tuning range Large tuning range junction varactor includes first and second junction capacitors coupled in parallel between first and second varactor terminals. First and second plates of the capacitors are formed by three alternating doped regions in a substrate. The second and...	06/22/2010
7727856	Selective STI stress relaxation through ion implantation A first example embodiment comprises the following steps and the structure formed therefrom. A trench having opposing sidewalls is formed within a substrate. A stress layer having an inherent stress is formed over the opposing trench sidewalls. The stress layer havi...	06/01/2010
7710182	Reliable level shifter of ultra-high voltage device used in low power application The present invention relates to integrated circuits. In particular, it relates to an IC comprising a receiving stage for receiving an input signal, an output stage for generating an output signal having a larger voltage range than the input signal and a level shift...	05/04/2010
7687381	Method of forming electrical interconnects within insulating layers that form consecutive sidewalls including forming a reaction layer on the inner sidewall Methods of forming integrated circuit device having electrical interconnects include forming an electrically insulating layer on a substrate and forming a hard mask on the electrically insulating layer. The hard mask and the electrically insulating layer are selecti...	03/30/2010
7678586	Structure and method to prevent charge damage from e-beam curing process An example embodiment is a method of curing a film over a semiconductor structure. We provide a semiconductor structure comprised of a substrate and an interconnect structure. We provide a film over the semiconductor structure. We provide an electron source, an anod...	03/16/2010
7674562	Angled-wedge chrome-face wall for intensity balance of alternating phase shift mask A method for forming a phase shift mask is presented. The method includes providing a substrate including a transparent material having first, second and third regions, the third region being disposed between the first and second regions. The method also includes fo...	03/09/2010
7672748	Automated manufacturing systems and methods An efficient manufacturing automation system and method is described. The system and method include bays, with each bay having a group of tools. Temporary storage locations are provided. A transport system facilitates movement of materials from the tools. The system...	03/02/2010
7670946	Methods to eliminate contact plug sidewall slit A method to form a barrier layer and contact plug using a touch up RIE. In a first embodiment, we form a first barrier layer over the dielectric layer and the substrate in the contact hole. The first barrier layer is comprised of Ta. A second barrier layer is formed...	03/02/2010
7659174	Method to enhance device performance with selective stress relief A structure and method of fabrication of a semiconductor device having a stress relief layer under a stress layer in one region of a substrate. In a first example, a stress relief layer is formed over a first region of the substrate (e.g., PFET region) and not over ...	02/09/2010

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Assignee: Chartered Semiconductor Manufacturing, Ltd.