Celebrity Inventors
Actress Jamie Lee Curtis is a patented inventor - she created a diaper equipped with a premoistened baby wipe. And that's no act!
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 6410429 | Method for fabricating void-free epitaxial-CoSi2 with ultra-shallow junctions A method for forming a void-free epitaxial cobalt silicide (CoSi2) layer on an ultra-shallow source/drain junction. A patterned silicon structure is cleaned using HF. A first titanium layer, a cobalt layer, and a second titanium layer are succe... | 06/25/2002 |
| 6406975 | Method for fabricating an air gap shallow trench isolation (STI) structure A method of manufacturing a shallow trench isolation (STI) with an air gap that is formed by decomposing an organic filler material through a cap layer. A pad layer and a barrier layer are formed over the substrate. The pad layer and the barrier layer are... | 06/18/2002 |
| 6380106 | Method for fabricating an air gap metallization scheme that reduces inter-metal capacitance of interconnect structures A method of manufacturing a metallization scheme with an air gap formed by vaporizing a filler polymer material. The filler material is covered by a critical permeable dielectric layer. The method begins by forming spaced conductive lines over a semicondu... | 04/30/2002 |
| 6380087 | CMP process utilizing dummy plugs in damascene process A method of fabricating a semiconductor wafer having at least one integrated circuit, the method comprising the following steps. A semiconductor wafer structure having at least an upper and a lower dielectric layer is provided. The semiconductor wafer str... | 04/30/2002 |
| 6380084 | Method to form high performance copper damascene interconnects by de-coupling via and metal line filling A method to form robust dual damascene interconnects by decoupling via and connective line trench filling has been achieved. A first dielectric layer is deposited overlying a silicon nitride layer. A shielding layer is deposited. The shielding layer, the ... | 04/30/2002 |
| 6358821 | Method of copper transport prevention by a sputtered gettering layer on backside of wafer A method of preventing copper transport on a semiconductor wafer, comprising the following steps. A semiconductor wafer having a front side and a backside is provided. Metal, selected from the group comprising aluminum, aluminum-copper, aluminum-silicon, ... | 03/19/2002 |
| 6348407 | Method to improve adhesion of organic dielectrics in dual damascene interconnects This invention relates to a method of fabrication used for semiconductor integrated circuit devices, and more specifically to the use an alternate etch stop in dual damascene interconnects that improves adhesion between low dielectric constant organic mat... | 02/19/2002 |
| 6313008 | Method to form a balloon shaped STI using a micro machining technique to remove heavily doped silicon The invention describes three embodiments of methods for forming a balloon shaped STI trench. The first embodiment begins by forming a barrier layer over a substrate. An isolation opening is formed in the barrier layer. Next, ions are implanted into said ... | 11/06/2001 |
| 6306714 | Method to form an elevated S/D CMOS device by contacting S/D through the contact of oxide A method of fabrication of an elevated source/drain (S/D) for a MOS device. A first insulating layer having a gate opening and source/drain openings is formed over a substrate. We form a LDD resist mask having opening over the source/drain openings over t... | 10/23/2001 |
| 6303449 | Method to form self-aligned elevated source/drain by selective removal of gate dielectric in the source/drain region followed by poly deposition and CMP A method of manufacturing a self aligned elevated source/drain (S/D). A first insulating layer is formed over a substrate. The first insulating layer having at least a gate opening and source/drain (S/D) openings adjacent to the gate opening. Spacer porti... | 10/16/2001 |
| 6300177 | Method to form transistors with multiple threshold voltages (VT) using a combination of different work function gate materials A method of forming a gate electrode, comprising the following steps. A semiconductor substrate having an overlying patterned layer exposing a portion of the substrate within active area and patterned layer opening. The patterned layer having exposed side... | 10/09/2001 |
| 6284603 | Flash memory cell structure with improved channel punch-through characteristics A new method of fabricating a Flash EEPROM memory cell is achieved. Ions are optionally implanted into said semiconductor substrate to form threshold enhancement regions of the same type as the semiconductor substrate. A tunneling oxide is formed. A first... | 09/04/2001 |
