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| Number | Title | Issue Date |
| 8106462 | Balancing NFET and PFET performance using straining layers An integrated circuit structure includes a substrate and at least one pair of complementary transistors on or in the substrate. The pair of complementary transistors comprises a first transistor and a second transistor. The structure also includes a first stress-pro... | 01/31/2012 |
| 8058176 | Methods of patterning insulating layers using etching techniques that compensate for etch rate variations Methods of forming integrated circuit devices include forming an integrated circuit substrate having an electrically insulating layer thereon and forming a mask layer pattern having at least first and second openings of different size therein, on the electrically in... | 11/15/2011 |
| 8026166 | Interconnect structures comprising capping layers with low dielectric constants and methods of making the same Interconnect structures comprising capping layers with low dielectric constants and good oxygen barrier properties and methods of making the same are provided. In one embodiment, the integrated circuit structure comprises: an interlevel dielectric layer disposed abo... | 09/27/2011 |
| 7994010 | Process for fabricating a semiconductor device having embedded epitaxial regions A process for fabricating a semiconductor device, such as a strained-channel transistor, includes forming epitaxial regions in a substrate in proximity to a gate electrode in which the surface profile of the epitaxial regions is defined by masking sidewall spacers a... | 08/09/2011 |
| 7977185 | Method and apparatus for post silicide spacer removal A method (and apparatus) of post silicide spacer removal includes preventing damage to the silicide spacer through the use of at least one of an oxide layer and a nitride layer. ... | 07/12/2011 |
| 7955936 | Semiconductor fabrication process including an SiGe rework method A method for fabricating a semiconductor device includes forming an SiGe region. The SiGe region can be an embedded source and drain region, or a compressive SiGe channel layer, or other SiGe regions within a semiconductor device. The SiGe region is exposed to an SC... | 06/07/2011 |
| 7935593 | Stress optimization in dual embedded epitaxially grown semiconductor processing Embodiments of the present disclosure provide stress optimization during manufacturing of dual embedded epitaxially grown (EPI) semiconductor structures using just two masks, such as nFET and pFET open for embedded epitaxial using SiC and SiGe, and separated halo im... | 05/03/2011 |
| 7928020 | Method of fabricating a nitrogenated silicon oxide layer and MOS device having same A method for fabricating a nitrogen-containing dielectric layer and semiconductor device including the dielectric layer in which a silicon oxide layer is formed on a substrate, such that an interface region resides adjacent to substrate and a surface region resides ... | 04/19/2011 |
| 7926000 | Integrated circuit system employing dipole multiple exposure An integrated circuit system that includes: providing a first mask including a first feature; exposing the first mask to a radiation source to form an image of the first feature on a photoresist material that is larger than a structure to be formed, the photoresist ... | 04/12/2011 |
| 7902548 | Planar voltage contrast test structure An integrated circuit and e-beam testing method are disclosed. The integrated circuit includes a test structure with a ground grid, a metal pad having a space therein and positioned within the ground grid, and a metal line connected to the ground grid and positioned... | 03/08/2011 |
| 7888224 | Method for forming a shallow junction region using defect engineering and laser annealing A method for forming a shallow junction region in a crystalline semiconductor substrate and method for fabricating a semiconductor device having the shallow junction region includes a defect engineering step in which first ions are introduced into a first region of ... | 02/15/2011 |
| 7879732 | Thin film etching method and semiconductor device fabrication using same A method for etching a thin film and fabricating a semiconductor device includes etching the thin film on a substrate, while monitoring the removal of an endpoint detection layer remotely located from the substrate, such that precise control of the thin film etching... | 02/01/2011 |
| 7867835 | Integrated circuit system for suppressing short channel effects An integrated circuit system that includes: providing a substrate including an active device with a gate and a gate dielectric; forming a first liner, a first spacer, a second liner, and a second spacer adjacent the gate; forming a material layer over the integrated... | 01/11/2011 |
| 7867698 | Reticle system for manufacturing integrated circuit systems A reticle system that includes: providing a reticle system; and assigning two or more of an image pattern onto the reticle system to form one or more layers of an integrated circuit system by grouping and pairing each of the image pattern onto the reticle system acc... | 01/11/2011 |
| 7866224 | Monitoring structure Apparatus is provided for determining presence of contamination on a lithography mask, including: a fluid trap having a base and at least one wall member extending substantially perpendicularly to the base for trapping fluid on a portion of the base when fluid intro... | 01/11/2011 |
| 7836420 | Integrated circuit system with assist feature An integrated circuit system comprising: providing a substrate; forming a main feature using a first non-cross-junction assist feature over the substrate; forming the main feature using a second non-cross-junction assist feature, adjacent a location of the first non... | 11/16/2010 |
| 7833888 | Integrated circuit system employing grain size enlargement An integrated circuit system that includes: providing a substrate including an active device with a gate top surface exposed; implanting a do pant within the gate to alter the grain size of the gate material; forming a dielectric layer over the active device and the... | 11/16/2010 |
| 7816274 | Methods for normalizing strain in a semiconductor device The electrical performance enhancing effects of inducing strain in semiconductor devices is made substantially uniform across a substrate having a varying population density of device components by selectively spacing apart the strain-inducing structures from the ef... | 10/19/2010 |
| 7795680 | Integrated circuit system employing selective epitaxial growth technology An integrated circuit system that includes: providing a substrate; depositing a dielectric on the substrate; depositing an isolation dielectric on the dielectric; forming a trench through the isolation dielectric and the dielectric to expose the substrate; depositin... | 09/14/2010 |
| 7795104 | Method for fabricating device structures having a variation in electrical conductivity A method for forming device structures having a variation in electrical conductivity includes forming a device structure and a radiation absorbing layer overlying the device structure. The radiation absorbing layer has a spatial variation and radiation absorbing cha... | 09/14/2010 |
| 7781895 | Via electromigration improvement by changing the via bottom geometric profile An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion b... | 08/24/2010 |
| 7772071 | Strained channel transistor and method of fabrication thereof The present invention relates to semiconductor integrated circuits. More particularly, but not exclusively, the invention relates to strained channel complimentary metal oxide semiconductor (CMOS) transistor structures and fabrication methods thereof. A strained cha... | 08/10/2010 |
| 7759207 | Integrated circuit system employing stress memorization transfer An integrated circuit system that includes: providing a gate and a spacer formed over a substrate; performing an implant that amorphizes the gate and a source/drain region defined by the spacer; removing the spacer; depositing a stress memorization layer over the in... | 07/20/2010 |
| 7759206 | Methods of forming semiconductor devices using embedded L-shape spacers A method of forming a semiconductor device that embeds an L-shaped spacer is provided. The method includes defining an L-shaped spacer on each side of a gate region of a substrate and embedding the L-shaped spacers in an oxide layer so that the oxide layer extends o... | 07/20/2010 |
| 7749894 | Integrated circuit processing system An integrated circuit processing system is provided including providing a substrate having an integrated circuit, forming an interconnect layer over the integrated circuit, applying a low-K dielectric layer over the interconnect layer, applying an ultra low-K dielec... | 07/06/2010 |
| 7741719 | Integrated circuit system with dummy region An integrated circuit system comprised by forming a first region, a second region and a third region within a dielectric over a substrate. The first region includes tungsten plugs. The second region is formed adjacent at least a portion of the perimeter of the first... | 06/22/2010 |
| 7737029 | Methods of forming metal interconnect structures on semiconductor substrates using oxygen-removing plasmas and interconnect structures formed thereby Methods of forming devices include forming a first electrically insulating layer having a metal interconnection therein, on a substrate and then forming a first electrically insulating barrier layer on an upper surface of the metal interconnection and on the first e... | 06/15/2010 |
| 7721414 | Method of manufacturing 3-D spiral stacked inductor on semiconductor material A method of manufacturing a 3-D spiral stacked inductor is provided having a substrate with a plurality of turns in a plurality of levels wherein the number of levels increases from an inner turn to the outer turn of the inductor. First and second connecting portion... | 05/25/2010 |
| 7692213 | Integrated circuit system employing a condensation process An integrated circuit system that includes: providing a PFET device including a PFET gate and a PFET gate dielectric; forming a source/drain extension from a first epitaxial layer aligned to a first PFET gate sidewall spacer; and forming a source/drain from a second... | 04/06/2010 |
| 7691739 | Via electromigration improvement by changing the via bottom geometric profile An integration approach to improve electromigration resistance in a semiconductor device is described. A via hole is formed in a stack that includes an upper dielectric layer, a middle TiN ARC, and a lower first metal layer and is filled with a conformal diffusion b... | 04/06/2010 |
| 7649612 | Phase shifting photolithography system A phase shifting photolithography system includes inserting a phase shift component in a path of an illumination, wherein the phase shift component modifies a portion of the illumination to a different, and controlling an aperture shutter of the phase shift componen... | 01/19/2010 |
| 7622403 | Semiconductor processing system with ultra low-K dielectric A semiconductor processing system with ultra low-K dielectric is provided including providing a substrate having an electronic circuit, forming an ultra low-K dielectric layer, having porogens, over the substrate, blocking an incoming radiation from a first region o... | 11/24/2009 |
| 7615484 | Integrated circuit manufacturing method using hard mask An integrated circuit hard mask processing system is provided including providing a substrate having an integrated circuit; forming an interconnect layer over the integrated circuit; applying a low-K dielectric layer over the interconnect layer; applying a hard mask... | 11/10/2009 |
| 7615417 | Triggered silicon controlled rectifier for RF ESD protection An ESD protection circuit is formed at the input/output interface contact of an integrated circuit to protect the integrated circuit from damage caused by an ESD event. The ESD protection circuit has a polysilicon bounded SCR connected between a signal input/output ... | 11/10/2009 |
| 7573081 | Method to fabricate horizontal air columns underneath metal inductor A new method is provided for creating an inductor on the surface of a silicon substrate. The invention provides overlying layers of oxide fins beneath a metal inductor. The oxide fins provide the stability support for the overlying metal inductor while also allowing... | 08/11/2009 |
| 7562318 | Test structure for automatic dynamic negative-bias temperature instability testing The invention describes a novel test structure and process to create the structure for performing automatic dynamic stress testing of PMOS devices for Negative Bias Temperature Instability (NB TI). The invention consists of an integrated inverter, two integrated ele... | 07/14/2009 |
| 7560199 | Polarizing photolithography system A polarizing photolithography reticle system is provided including providing a reticle substrate, forming polarization structures on the reticle substrate, and etching circuit patterns on the reticle substrate on a side opposite the polarization structures. ... | 07/14/2009 |
| 7556891 | Method and apparatus for contact hole unit cell formation A method for forming a contact hole unit cell is provided. A light transparent contact hole region of a first phase is positioned at a first plane. A light transparent phase-shifting region of a second phase is positioned at the first plane, the second phase being s... | 07/07/2009 |
| 7553758 | Method of fabricating interconnections of microelectronic device using dual damascene process Method of Fabricating Interconnections of a Microelectronic Device Using a Dual Damascene Process. A method of fabricating interconnections of a microelectronic device includes preparing a semiconductor substrate comprising a lower dielectric layer and a lower inter... | 06/30/2009 |
| 7541288 | Methods of forming integrated circuit structures using insulator deposition and insulator gap filling techniques Methods of forming integrated circuit devices include depositing an electrically insulating layer onto an integrated circuit substrate having integrated circuit structures thereon. This deposition step results in the formation of an electrically insulating layer hav... | 06/02/2009 |
