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| Number | Title | Issue Date |
| 7587579 | Processor core interface for providing external hardware modules with access to registers of the core and methods thereof A processor core architecture includes a cluster having at least a register file and predefined functional units having access to the register file. The architecture also includes an interface to one or more arbitrary functional units external to the processor core.... | 09/08/2009 |
| 7555511 | Methods for addressing input data values of a Fast Fourier Transform (FFT) calculation A method for the generation of addresses of successive pairs of input data values of stages of a Fast Fourier Transform calculation stored contiguously in a memory includes initializing at most once per stage a first base address pointer to an address of a first inp... | 06/30/2009 |
| 7412473 | Arithmetic circuitry for averaging and methods thereof A functional unit includes one or more instances of arithmetic circuitry for calculating averages. Each instance of arithmetic circuitry includes first, second and third adders, each having first and second inputs and an output that is a sum of the first and second ... | 08/12/2008 |
| 7149768 | 3-input arithmetic logic unit A 3-input adder/subtractor unit, having a first input for receiving a first operand A, a second input for receiving a second operand B, and a third input for receiving a third operand C. An add/subtract unit includes a control input for receiving a user-specified op... | 12/12/2006 |
| 7031407 | Apparatus and method for decoding and trace back of convolution codes using the viterbi decoding algorithm A system for generating and storing trace bits for Viterbi decoding of binary convolution codes includes at least one arithmetic logic unit (ALU) for determining the trace bits, and a first register and a second register for storing the trace bits. The first registe... | 04/18/2006 |
| 6988117 | Bit-reversed indexing in a modified harvard DSP architecture A method for indexing a plurality of ordered elements stored in bit-reversed order in a first and a second memory space, the first memory space indexed by a first memory index denoting memory positions in the first memory space, the second memory space indexed by a ... | 01/17/2006 |
| 6868186 | Visual lossless image compression An image compression method is provided including separating an image into a plurality of color channel sub-images processing each of the color channel sub-images by sub-sampling the sub-image transform coding the sub-sampled sub-image decoding the transform-coded i... | 03/15/2005 |
| 6760880 | Scalar product and parity check An apparatus includes a plurality of AND gates each to receive as input a bit of a first binary vector and a corresponding bit of a second binary vector, where the length of the first binary vector is not greater than the length of the second binary vector. The appa... | 07/06/2004 |
