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| Number | Title | Issue Date |
| 8122401 | System, method, and computer program product for determining equivalence of netlists utilizing at least one transformation A system, method and computer program product are provided for determining equivalence of netlists utilizing at least one transformation. In use, a netlist including a plurality of infinite portions and a plurality of finite portions is identified. Additionally, at ... | 02/21/2012 |
| 8117571 | System, method, and computer program product for determining equivalence of netlists utilizing abstractions and transformations A system, method and computer program product are provided for determining equivalence of netlists utilizing at least one transformation. In use, a netlist including a plurality of infinite portions and a plurality of finite portions is identified. Additionally, at ... | 02/14/2012 |
| 8037443 | System, method, and computer program product for optimizing an altered hardware design utilizing power reports A system, method and computer program product are provided for optimizing an altered hardware design utilizing power reports. In use, a first hardware design is synthesized. Additionally, a first power report is generated for the synthesized first hardware design. F... | 10/11/2011 |
| 7966593 | Integrated circuit design system, method, and computer program product that takes into account the stability of various design signals An integrated circuit design system, method, and computer program product are provided that takes into account signal stability. In use, at least one condition is identified where an output of a logic element before receipt of a clock signal is the same as the outpu... | 06/21/2011 |
| 7761827 | Integrated circuit design system, method, and computer program product that takes into account observability based clock gating conditions An integrated circuit design system, method, and computer program product are provided that takes into account observability based clock gating conditions. In use, at least one condition is identified where an output of a first logic element is not a function of a f... | 07/20/2010 |
| 7673257 | System, method and computer program product for word-level operator-to-cell mapping A mapping system, method and computer program product are provided. In use, at least one arithmetic operator is received. Further, the at least one arithmetic operator is mapped to at least one cell, at a word-level. ... | 03/02/2010 |
| 7607115 | System, method and computer program product for timing-independent sequential equivalence verification A system, method and computer program product are provided for verifying sequential equivalence. In use, input is fed to a first system and a second system in a timing-independent manner to generate output. To this end, sequential equivalence of the first system and... | 10/20/2009 |
| 7539956 | System and computer program product for simultaneous cell identification/technology mapping A system, method and computer program product are provided for simultaneous cell identification/technology mapping. In use, a plurality of data operators is received. Further, at least two cells are identified for each data operator, simultaneously with technology m... | 05/26/2009 |
| 7350168 | System, method and computer program product for equivalence checking between designs with sequential differences A system, method and computer program product are provided for equivalency checking between a first design and a second design having sequential differences. To accomplish the equivalency checking, sequential differences between a first design and a second design ar... | 03/25/2008 |
| 7333032 | System, method and computer program product for word-level computations and storage A system, method and computer program product are provided for generating and manipulating a compressed data structure. Initially, a plurality of values associated with an ordered collection of bits is received. It is then determined which of the values are the same... | 02/19/2008 |
| 7287235 | Method of simplifying a circuit for equivalence checking A method of simplifying a logic circuit for enabling cycle-by-cycle equivalence checking is provided. To accomplish this, first, a logic circuit is identified to be a variable delay circuit or a fixed delay circuit. If the logic circuit is a variable delay circuit, ... | 10/23/2007 |
| 7284218 | Method and system for inplace symbolic simulation over multiple cycles of a multi-clock domain design A method and a system for inplace symbolic simulation of circuits. This method is applicable to both single clock and multiple clock domain designs. The method performs inplace symbolic simulation by appending slots to the various objects of the circuit. The slot as... | 10/16/2007 |
