Bizarre Patents
An armor with rollers is provided that enables a user to move in all positions by rolling on a hard and smooth surface while constantly varying his bearing points on the ground.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8181137 | Layout versus schematic error system and method According to various embodiments of the invention, systems and methods for presenting Layout Versus Schematic (LVS) errors within a layout using a visual circuit representation of the design and highlighting is provided. One embodiment includes overlaying the layout... | 05/15/2012 |
| 8180621 | Parametric perturbations of performance metrics for integrated circuits A method of simulating parametric variations in an integrated circuit (IC) includes: specifying an IC model, wherein the IC model includes one or more parameters for variation about a nominal condition; calculating parametric perturbations about the nominal conditio... | 05/15/2012 |
| 8176463 | Modeling and simulating device mismatch for designing integrated circuits A user specifies layout styles for devices in a circuit schematic, where the layout styles capture features of device arrangements and device correlations. The resulting layout can be simulated by using a computer so that one or more performance metrics can be evalu... | 05/08/2012 |
| 8166442 | Local preferred direction architecture Some embodiments of the invention provide a Local Preferred Direction (LPD) wiring model for use with one or more EDA tools (such as placing, routing, etc). An LPD wiring model allows at least one wiring layer to have a set of regions that each have a different pref... | 04/24/2012 |
| 8161502 | Method and apparatus for implementing a task-based interface in a logic verification system Method and apparatus for implementing a task-based interface in a logic verification system is described. In some examples, a task server and a context memory are implemented in a hardware accelerator for a task. The task server is configured for communication with ... | 04/17/2012 |
| 8161448 | Replicant simulation In one embodiment, a method comprises partitioning a circuit description into a plurality of simulateable partitions. The partitioning is independent of a hierarchy specified in the circuit definition. The method also comprises sorting the plurality of simulateable ... | 04/17/2012 |
| 8161439 | Method and apparatus for processing assertions in assertion-based verification of a logic design Method and apparatus for processing assertions in assertion-based verification of a logic design are described. One example relates to processing an assertion during verification of a logic design. An evaluation engine is generated that encodes, using a non-determin... | 04/17/2012 |
| 8161425 | Method and system for implementing timing aware metal fill An improved approach for implementing metal fill on an electrical device without causing creating cross-coupling capacitance problems is disclosed. Timing aware metal fill insertion is performed to avoid or minimize cross-capacitance problems on the IC design. A cos... | 04/17/2012 |
| 8161423 | Defect filtering optical verification process An apparatus and method for optical lithography verification includes filtering a lithography simulation of proposed sub-lightwave pattern formations during at feast one design phase or manufacturing phase of an article of manufacture having sub-lightwave structures... | 04/17/2012 |
| 8160862 | Method and apparatus for controlling power in an emulation system Method and apparatus for controlling power in an emulation system is described. In one example, power is controlled in a processor-based emulation system coupled to a host computer. A logic design is processed to identify unused resources in the emulation system dur... | 04/17/2012 |
| 8160860 | Method and apparatus for event-based simulation of a digital design having a power shut-off feature Method, apparatus, and computer readable medium for simulating a logic design having power domains are described. In some examples, a switchable power domain of the power domains is identified, the switchable power domain having primary inputs and having a power sta... | 04/17/2012 |
| 8160858 | Systems and methods of efficient library characterization for integrated circuit cell libraries A method of efficient library characterization of a circuit of a logic gate having a plurality of transistors and a plurality of nodes defining interconnection points in the circuit is disclosed. The method includes determining a plurality of vectors for a plurality... | 04/17/2012 |
| 8156474 | Automation of software verification A method, system, and computer program product are disclosed for automatic test generation for a compiler. In one approach, the method, system and computer program product represent a test case for the compiler in a structure with one or more elements of a programmi... | 04/10/2012 |
| 8156453 | Method and system identifying and locating IP blocks and block suppliers for an electronic design An improved approach for locating and identifying IP for an electronic design is described. The present approach addresses the situation in which an IP catalog does not contain any IP which matches the exact requirements of an electronic design for which the IP is t... | 04/10/2012 |
| 8156450 | Method and system for mask optimization A method and apparatus for mask optimization is provided. Mask design and production is optimized by providing proper weighting parameters for critical features. The parameters may include information such as parametric information, functional information, and hot s... | 04/10/2012 |
| 8151239 | Method for resolving overloads in autorouting physical interconnections Overloaded regions in the routing space of a physical network are resolved via a routing procedure composed of a topological routing phase and a geometric routing phase. The overloads are resolved in the topological routing phase where the constraints of routing are... | 04/03/2012 |
| 8151229 | System and method of computing pin criticalities under process variations for timing analysis and optimization A system and method for determining the criticality of each timing pin in a circuit design are disclosed. The criticality of a timing pin is the probability that the timing pin is on the path with the worst slack in the circuit design. According to the methodology, ... | 04/03/2012 |
| 8151219 | System and method for multi-exposure pattern decomposition Some embodiments provide a method and system for identifying error markers for patterns within a design layout that do not meet the manufacturing constraints. Some embodiments extend a region from the error marked region to extract a pattern for decomposition analys... | 04/03/2012 |
| 8146042 | Method and system for optimized circuit autorouting An approach is provided for selectively optimizing a circuit design to be physical implemented. The approach includes generating a circuit routing solution in accordance with a plurality of constraints for parametric resources of the circuit design, with the constra... | 03/27/2012 |
| 8146024 | Method and system for process optimization A method and apparatus for process optimization is provided. Process optimization improves parametric and functional yield post mask manufacturing. ... | 03/27/2012 |
| 8145458 | Method and system for automatic stress analysis of analog components in digital electronic circuit An automated approach is provided for evaluating stress upon analog components embedded in a digital electronic circuit design. The approach includes establishing a computer readable circuit definition of the digital electronic circuit design. The circuit definition... | 03/27/2012 |
| 8141008 | Optical lithography correction process A apparatus and method for correcting a process critical layout includes characterizing the influence of individual ones of a set of worst case process variations on a simulated nano-circuit layout design and then correcting layout geometries in the simulated nano-c... | 03/20/2012 |
| 8136068 | Methods, systems, and computer program products for implementing compact manufacturing models in electronic design automation Disclosed are a method, a system, and a computer program product for implementing compact manufacturing model during various stages of electronic circuit designs. In some embodiments, the method or the system receives or identifies physics based data. In some embodi... | 03/13/2012 |
| 8136060 | Method and mechanism for identifying and tracking shape connectivity A method and mechanism is disclosed for identifying and tracking nets in an electrical design. A hierarchical design does not have to be flattened to perform the operation of identifying and tracking nets. To identify sets of connected shapes, instead of having to u... | 03/13/2012 |
| 8136056 | Method and system for incorporation of patterns and design rule checking Methods and systems for representing the limitations of a lithographic process using a pattern library instead of, or in addition to, using design rules. The pattern library includes “known good” patterns, which chip fabricators know from experience are successf... | 03/13/2012 |
| 8132135 | Method and system for creating a boolean model of multi-path and multi-strength signals for verification A system, method, computer program product for verification and equivalence checking. In one approach, the system, method, and computer program product analyzes the switching paths in a manner consistent with circuit functionality to provide a complete application w... | 03/06/2012 |
| 8127260 | Physical layout estimator In one embodiment of the invention, a physical layout wire-load algorithm is used to generate a wire-load model based on physical data including aspect ratio and wire definitions defined in a physical library. The physical layout estimator is utilized to dynamically... | 02/28/2012 |
| 8122397 | Method and system for mapping source elements to destination elements as interconnect routing assignments Aspects for optimized mapping of source elements to destination elements as interconnect routing assignments are described. The aspects include utilizing chosen rules to establish a priority for mapping, and generating mapping assignments based on the priority. The ... | 02/21/2012 |
| 8122392 | Robust design using manufacturability models The present invention allows for a robust design using manufacturability models. A method, system and/or computer usable medium may be provided in an integrated circuit design to track sensitivity to a variation of process from wafer to wafer and/or fab to fab in or... | 02/21/2012 |
| 8122389 | Apparatus and method for segmenting edges for optical proximity correction An apparatus and method for modifying a mask data set includes calculating a derivative of a figure-of-merit, indicative of a data set defined by a plurality of polygon edges and then segmenting polygon edges in response to said step of calculating. ... | 02/21/2012 |
| 8120378 | System to control insertion of care-bits in an IC test vector improved optical probing Systems, methods, and computer readable media storing instructions for such methods relate to generating test vectors that can be used for exercising a particular area of interest in an integrated circuit. The test vectors generally include a non-overlapping repeati... | 02/21/2012 |
| 8117569 | Method and mechanism for implementing a minimum spanning tree Disclosed is an improved method, system, and mechanism for using and constructing a minimum spanning tree. In one approach, each iteration of the process for constructing a minimum spanning tree calculates at most two additional point-pairs for nearest neighbors of ... | 02/14/2012 |
| 8117566 | Method and system for representing manufacturing and lithography information for IC routing A mechanism to compress manufacturing awareness into a small representation and to enable the router to consult the representation without performing, or understanding, detailed process analysis, is disclosed. ... | 02/14/2012 |
| 8112733 | Method and apparatus for routing with independent goals on different layers Some embodiments of the invention provide a method of routing. The method selects a net with a set of routable elements in a multi-layer layout region. In some embodiments, the method identifies a route for the net based on different congestion goals on different la... | 02/07/2012 |
| 8108878 | Method and apparatus for detecting indeterminate dependencies in a distributed computing environment Method and system for detecting indeterminate dependencies in a distributed computing grid. A determination is made whether a deadlock situation exists within a workflow of the distributed computing grid and a user of the computing grid is notified of the deadlock s... | 01/31/2012 |
| 8108194 | Peak power detection in digital designs using emulation systems A method of analyzing power consumption for a DUT (device under test) that includes an integrated circuit or an electronic system includes: providing emulation data for states of the DUT in one or more time windows; determining operational mode values from the emula... | 01/31/2012 |
| 8104007 | Method and apparatus for thermal analysis Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit (“IC”) design layout that includes numerous circuit modules. The method divides the IC design layout into a set of elements, where at least one element in... | 01/24/2012 |
| 8104006 | Method and apparatus for thermal analysis Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit (“IC”) layout that includes numerous circuit modules. In some embodiments, the method initially defines several power dissipation equations that express t... | 01/24/2012 |
| 8104001 | Automated debugging method for over-constrained circuit verification environment An automated debugging method and system for over-constrained circuit verification environment are described. Useful information related to circuit evaluation and/or over-constrained event is collected and provided. The information may include: clock cycles at which... | 01/24/2012 |
| 8103996 | Method and apparatus for thermal analysis of through-silicon via (TSV) Some embodiments of the invention provide a method for performing thermal analysis of an integrated circuit (“IC”) design layout. The IC design layout includes several wiring layers in some embodiments. The IC design layout includes a substrate that has at least... | 01/24/2012 |
