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| Number | Title | Issue Date |
| 6044206 | Out of order instruction processing using dual memory banks A process of synchronizing two execution units sharing a common memory with a plurality of memory banks starts by assigning a first memory bank to a one of two execution units. The other memory bank is assigned to the other execution unit. Then a sequence... | 03/28/2000 |
| 5929902 | Method and apparatus for inverse telecine processing by fitting 3:2 pull-down patterns The invention provides methods and apparatus for performing inverse telecine processing on an input video frame sequence to be encoded. A method well-suited for detelecine of film-only telecine in MPEG-1 or MPEG-2 applications includes the steps of attemp... | 07/27/1999 |
| 5909187 | Current steering circuit for a digital-to-analog converter An improved current steering cell for a DAC which eliminates the need for an inverter reduces the noise at the common mode. The cell includes a first and a second current steering MOS transistor of a first polarity type, each having a gate and a pair of c... | 06/01/1999 |
| 5889949 | Processing system with memory arbitrating between memory access requests in a set top box A method and apparatus for providing memory arbitration which allows multiple hardware functions implemented in a single ASIC to utilize a single shared memory unit or multiple shared memory units. The memory arbitration technique establishes a priority a... | 03/30/1999 |
| 5886657 | Selectable reference voltage circuit for a digital-to-analog converter A selectable reference voltage circuit for a digital-to-analog converter (DAC) which includes an input terminal for receiving an external reference voltage, a voltage comparator having two inputs and an output, one input for receiving the reference voltag... | 03/23/1999 |
| 5878166 | Field frame macroblock encoding decision A rate control algorithm for an MPEG-2 compliant encoder is described. The rate control algorithm has embodiments useful for constant bit rate and variable bit rate encoding. In particular, the invention relates to a field frame macroblock encoding decisi... | 03/02/1999 |
| 5872598 | Scene change detection using quantization scale factor rate control A rate control algorithm for an MPEG-2 compliant encoder is described. The rate control algorithm has embodiments useful for constant bit rate and variable bit rate encoding. In particular, the invention relates to scene change detection.... | 02/16/1999 |
| 5870497 | Decoder for compressed video signals A decoder for compressed video signals comprises a central processing unit (CPU), a dynamic random access memory (DRAM) controller, a variable length code (VLC) decoder, a pixel filter and a video output unit. The microcoded CPU performs dequantization an... | 02/09/1999 |
| 5815646 | Decompression processor for video applications A method and structure including four video decompression structures and eight memory banks are provided for decoding high definition television (HDTV) signal. In this HDTV decompression structure, the 1920×1080 pixel display space is divided into four v... | 09/29/1998 |
| 5771316 | Fade detection A rate control algorithm for an MPEG-2 compliant encoder is described. The rate control algorithm has embodiments useful for constant bit rate and variable bit rate encoding. In particular, the invention relates to fade detection.... | 06/23/1998 |
| 5686963 | Method for performing rate control in a video encoder which provides a bit budget for each frame while employing virtual buffers and virtual buffer verifiers A rate control algorithm for an MPEG-2 compliant encoder. The rate control has embodiments useful for constant bit rate and variable bit rate encoding of video frames. The present invention relates to statistical multiplexing, virtual buffers and virtual ... | 11/11/1997 |
| 5633687 | Method and system for providing an interlaced image on an display A system and method for removing motion artifacts from an interlaced image is disclosed. The interlaced image comprises an odd and an even field. The system and method includes providing one of the odd and the even fields on every other line of the displa... | 05/27/1997 |
| 5598514 | Structure and method for a multistandard video encoder/decoder A structure and a format provide a video signal encoder under the MPEG (Motion Picture Experts Group) standard. In one embodiment, the video signal interface is provided with a decimator for providing input filtering for the incoming signals. In one embod... | 01/28/1997 |
| 5423010 | Structure and method for packing and unpacking a stream of N-bit data to and from a stream of N-bit data words A structure and a method capable of both packing data into and unpacking data from either the little endian or the big endian format are provided. Under the structure and method of the present invention, the packed or unpacked data, as the case may be, is... | 06/06/1995 |
| 5379356 | Decompression processor for video applications A method and a structure are provided to decode intraframe and interframe coded compressed video data. In one embodiment, a decompression structure having a processor is provided with a global bus over which a decoder coprocessor, an inverse discrete cosi... | 01/03/1995 |
| 5309567 | Structure and method for an asynchronous communication protocol between master and slave processors In accordance with the present invention, a structure and a method for asynchronously interfacing a master processor and a slave processor is provided by receiving from and providing to the master device control signals of a polling protocol, and receivin... | 05/03/1994 |
| 5270832 | System for compression and decompression of video data using discrete cosine transform and coding techniques A digital video compression system and an apparatus implementing this system are disclosed. Specifically, matrices of pixels in the RGB signal format are converted into YUV representation, including a step of selectively sampling the chrominance component... | 12/14/1993 |
| 5191548 | System for compression and decompression of video data using discrete cosine transform and coding techniques A method and a structure provide discrete cosine transform (DCT) and its inverse (IDCT) using digital FIR filters in a filter bank. The filter bank of the present invention forms a structure of cascaded filters, in which data are communicated only between... | 03/02/1993 |
