Quotables
"What can be more palpably absurd than the prospect held out of locomotives traveling twice as fast as stagecoaches?"
The Quarterly Review ; March edition, 1825
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 7406406 | Instructions to load and store containing words in a computer system emulator with host word size larger than that of emulated machine Two unique instructions for the instruction set of a target 36-bit machine which is emulated on a host 64-bit machine are provided in order to achieve visibility, to an emulated application program, of a “containing” word stored in the memory of the host machine... | 07/29/2008 |
| 7314491 | Encapsulation of large native operating system functions as enhancements of the instruction set in an emulated central processor system This invention relates to the art of computer system emulation and, more particularly, to a computer system emulator in which the functions normally performed by the hardware in a legacy central processor unit are emulated by a software program. The invention is to ... | 01/01/2008 |
| 7219253 | Process for providing submodel performance in a computer processing unit A simple and accurate processor derating method includes: sampling a real-time counter/clock too obtain an initial time value T1; resetting an Icnt Counter; incrementing the Icnt Counter to reflect the processing of each instruction; comparing the count in th... | 05/15/2007 |
| 7082551 | Method and data processing system providing checkpoint/restart across multiple heterogeneous computer systems Bulk data is read or written by an application on a first computer system to a file on a second heterogeneous computer system. Alternatively it is read or written as bulk data directly between applications on these heterogeneous systems. Jobs or tasks are started fr... | 07/25/2006 |
| 7024467 | Method and data processing system providing file I/O across multiple heterogeneous computer systems Bulk data is read or written by an application on a first computer system to a file on a second heterogeneous computer system. Alternatively it is read or written as bulk data directly between applications on these heterogeneous systems. Jobs or tasks are started fr... | 04/04/2006 |
| 6983429 | Formal proof methods for analyzing circuit loading problems under operating conditions A process for determining the optimum load driving capacity for each driving node in a complex logic circuit is disclosed. First, the logic equations of the logic circuit are extracted from a circuit description. Then, the fan-out of each driving node is analyzed to... | 01/03/2006 |
| 6973539 | Multiprocessor write-into-cache system incorporating efficient access to a plurality of gatewords A multiprocessor write-into-cache data processing system includes a feature for preventing hogging of ownership of a first gateword stored in the memory which governs access to a first common code/data set shared by processes running in the processors by imposing fi... | 12/06/2005 |
| 6970977 | Equal access to prevent gateword dominance in a multiprocessor write-into-cache environment In a multiprocessor write-into-cache data processing system including: a memory; at least first and second shared caches; a system bus coupling the memory and the shared caches; at least one processor having a private cache coupled, respectively, to each shared cach... | 11/29/2005 |
| 6938145 | Associative memory system with a multi-digit incrementable validity counter A computer system includes a central processing unit, an addressable main memory storing data pages and a page table, and an associative memory. The associative memory stores a plurality of entries in accordance with a low order virtual address component issued by t... | 08/30/2005 |
| 6922666 | Method and data processing system for performing atomic multiple word reads Atomic multiple word reads are provided when emulating a target system that supports atomic multiple word reads on a host system that does not. For each except the last word to be read, a gate flag is read using an advanced speculative load, and tested, until found ... | 07/26/2005 |
| 6915405 | Emulated target associative memory system with a multi-digit incrementable validity counter A host computer system, including an addressable main memory storing data pages and a page table, emulates a target computer system which includes an emulated target central processing unit, an emulated target associative memory and an emulated target multi-digit in... | 07/05/2005 |
| 6898738 | High integrity cache directory Cache memory, and thus computer system, reliability is increased by duplicating cache tag entries. Each cache tag has a primary entry and a duplicate entry. Then, when cache tags are associatively searched, both the primary and the duplicate entry are compared to th... | 05/24/2005 |
| 6895529 | Rebuilding “in-doubt” states reliably after multiple system failures in a data processing system performing two-phase transaction processing A data processing system participating in two-phase transaction processing operations which, when a system failure occurs while one or more transactions are in process, can successfully rebuild “in-doubt” states even when another system failure occurs during an ... | 05/17/2005 |
| 6868483 | Balanced access to prevent gateword dominance in a multiprocessor write-into-cache environment In a multiprocessor data processing system including: a main memory; at least first and second shared caches; a system bus coupling the main memory and the first and second shared caches; at least four processors having respective private caches with the first and s... | 03/15/2005 |
| 6779132 | Preserving dump capability after a fault-on-fault or related type failure in a fault tolerant computer system When a fault-on-fault condition arises in a data processing system which follows a backup fault procedure in the fault handling process, control is passed to dedicated firmware. Fault flags are reset and information vital to maintaining operating system control is s... | 08/17/2004 |
| 6763328 | Method and data processing system for emulating virtual memory utilizing threads In an emulation of a multiprocessor Target computer system on a Host computer system, Host virtual memory addresses are mapped and utilized as Target virtual memory addresses. Target virtual memory control tables are setup accordingly. Each Target processor is mappe... | 07/13/2004 |
| 6760811 | Gateword acquisition in a multiprocessor write-into-cache environment In a multiprocessor data processing system including: a memory, first and second shared caches, a system bus coupling the memory and the shared caches, first, second, third and fourth processors having, respectively, first, second, third and fourth private caches wi... | 07/06/2004 |
| 6754859 | Computer processor read/alter/rewrite optimization cache invalidate signals A plurality of processors in a data processing system share a common memory through which they communicate and share resources. When sharing resources, one processor needs to wait for another processor to modify a specified location in memory, such as unlocking a lo... | 06/22/2004 |
| 6728846 | Method and data processing system for performing atomic multiple word writes Atomic multiple word writes are provided when emulating a target system that supports atomic multiple word writes on a host system that does not. For each except the last word to be written, a gate flag is read, tested, and locked when it is found unlocked. The word... | 04/27/2004 |
| 6697959 | Fault handling in a data processing system utilizing a fault vector pointer table A fault number is utilized by microcode fault handling to index into a fault array pointer table containing a plurality of pointers to entry descriptors describing fault handling routines. The pointer resulting from the indexing is utilized to retrieve an... | 02/24/2004 |
| 6687845 | Fault vector pointer table A fault number is utilized by microcode fault handling to index into a fault array pointer table containing a plurality of pointers to entry descriptors describing fault handling routines. The pointer resulting from the indexing is utilized to retrieve an... | 02/03/2004 |
| 6665699 | Method and data processing system providing processor affinity dispatching A processor in a data processing system having multiple cache memories performs cache memory or processor module affinity dispatchin. Processes awaiting dispatch are stored in prioritized queues. Each queue has a priority chain, and a chain for each cache... | 12/16/2003 |
| 6615217 | Method and data processing system providing bulk record memory transfers across multiple heterogeneous computer systems Bulk data is read or written by an application on a first computer system to a file on a second heterogeneous computer system. Alternatively it is read or written as bulk data directly between applications on these heterogeneous systems. Jobs or tasks are... | 09/02/2003 |
| 6609246 | Integrated development environment for high speed transaction processing WWW applications on heterogeneous computer systems An integrated development environment on a client provides for developing transaction programs, web pages, and applets for execution on a high performance transactional based World Wide Web server. The transaction programs are developed on the client, the... | 08/19/2003 |
| 6606694 | Write logging in mirrored disk subsystems Disk drives are mirrored through duplication controlled by disk controllers. Each disk controller controls writing to a set of disk drives. A disk write request to one disk controller causes that disk controller to write to one of its disks and to transmi... | 08/12/2003 |
| 6604060 | Method and apparatus for determining CC-NUMA intra-processor delays In a Cache-Coherent Non-Uniform Memory Architecture (CC-NUMA), the time as measured in cycles that it takes for cache control signals to travel between processors (92) sharing an L2 cache (94) differs from the time it takes for those signals to travel bet... | 08/05/2003 |
| 6574748 | Fast relief swapping of processors in a data processing system In a data processing system with multiple processors, failing processors are replaced with spare processors. This allows the system to continue to operate without degradation. An intercept process is notified of a processor failure so that it can collect ... | 06/03/2003 |
| 6530076 | Data processing system processor dynamic selection of internal signal tracing A processor (92) contains a Trace RAM (210) for tracing internal processor signals and operands. A first trace mode separately traces microcode instruction execution and cache controller execution. Selectable groups of signals are traced from both the cac... | 03/04/2003 |
| 6529862 | Method and apparatus for dynamic management of translated code blocks in dynamic object code translation In a data processing system implementing Dynamic Object Code Translation (DOCT) for emulating Target system instructions on a Host system, each Target system instruction has an associated index/offset field and an associated code tag that identifies wheth... | 03/04/2003 |
| 6516295 | Method and apparatus for emulating self-modifying code In a data processing system implementing Dynamic Object Code Translation (DOCT) for emulating Target system instructions on a Host system, each Target system instruction has an associated index/offset field and an associated code tag that identifies wheth... | 02/04/2003 |
| 6484272 | Gate close balking for fair gating in a nonuniform memory architecture data processing system In a NUMA architecture, processors in the same CPU module with a processor opening a spin gate tend to have preferential access to a spin gate in memory when attempting to close the spin gate. This "unfair" memory access to the desired spin gate can resul... | 11/19/2002 |
| 6480845 | Method and data processing system for emulating virtual memory working spaces In an emulation of a multiprocessor Target computer system on a Host computer system, Host virtual memory addresses are mapped and utilized as Target virtual memory addresses. Target virtual memory control tables are setup accordingly. Virtual-to-real add... | 11/12/2002 |
| 6459571 | Packaging system for mass memory units A mass memory storage unit includes a cabinet and one or more drawers incorporated into the cabinet. Each drawer is movable between closed and open positions to permit access to the interior for service. Inside each drawer, there is a connector plane disp... | 10/01/2002 |
| 6457171 | Storage structure for dynamic management of translated code blocks in dynamic object code translation In a data processing system implementing Dynamic Object Code Translation (DOCT) for emulating Target system instructions on a Host system, each Target system instruction has an associated index/offset field and an associated code tag that identifies wheth... | 09/24/2002 |
| 6449613 | Method and data processing system for hashing database record keys in a discontinuous hash table A method of addressing mass storage memory in which information is stored in Space Control Pages of physically contiguous disk segments subject to irregularities in the mapping is disclosed. Space Control Pages fall at regular intervals across the address... | 09/10/2002 |
| 6446094 | Data structure for emulating virtual memory working spaces In an emulation of a multiprocessor Target computer system on a Host computer system, Host virtual memory addresses are mapped and utilized as Target virtual memory addresses. Target virtual memory control tables are setup accordingly. Virtual-to-real add... | 09/03/2002 |
| 6446062 | Method and apparatus for improving the performance of a generated code cache search operation through the use of static key values A cache manager of a relational database management system (RDBMS) is able to bypass time consuming search operations through the use of a key memory structure and locate generated code segments within an SQL cache within a minimum of time. The SQL cache ... | 09/03/2002 |
| 6446034 | Processor emulation virtual memory address translation When emulating a Target architecture on a Host system having a different architecture, virtual to real address translation is typically expensive in terms of computer cycles. The cost can be significantly reduced by utilizing direct page table pointers to... | 09/03/2002 |
| 6442681 | Pipelined central processor managing the execution of instructions with proximate successive branches in a cache-based data processing system while performing block mode transfer predictions A cache used with a pipelined processor includes an instruction cache, instruction buffers for receiving instruction sub-blocks from the instruction cache and providing instructions to the pipelined processor, and a branch cache. The branch cache includes... | 08/27/2002 |
| 6442676 | Processor with different width functional units ignoring extra bits of bus wider than instruction width A data processing system contains a processor supporting both Narrow and Wide instructions and Narrow and Wide word size fixed-point and floating-point operands. The processor communicates over a bus utilizing a Wide word size with the remainder of the da... | 08/27/2002 |
