Bizarre Patents
An aircraft having vertical takeoff and landing capability provided with at least first and second laterally extending paddle wheels rotatable on a central axis perpendicular to the longitudinal axis of the aircraft fuselage and between its nose and tail.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 6075790 | Asynchronous transfer mode system for, and method of, writing a cell payload between a control queue on one side of a system bus and a status queue on the other side of the system bus A status queue in a host and a control queue in a segmentation and reassembly (SAR) subsystem are on opposite sides of a host bus in a control plane. Buffer descriptors in the host and the SAR and buffers in the host are in a data plane. To transfer cell ... | 06/13/2000 |
| 5974478 | System for command processing or emulation in a computer system, such as emulation of DMA commands using burst mode data transfer for sound A system and method for providing sound in a computer are disclosed. An audio module for controlling digitized sound I/O is included in a media stream controller. The media stream controller may also coordinate graphics and video which allows multiple med... | 10/26/1999 |
| 5949781 | Controller for ATM segmentation and reassembly A header and a payload in a cell are separated for transfer between a cell interface and a host memory. The header is transferred to a control memory. For transfer to the host memory, the control memory initially provides a host-memory region address and ... | 09/07/1999 |
| 5940610 | Using prioritized interrupt callback routines to process different types of multimedia information Multimedia information (e.g. graphics, video, sound, control information) passes through a system bus from a CPU main memory to a display memory in accordance with CPU commands. The information may be packetized with associated packet types identifying th... | 08/17/1999 |
| 5812204 | System and method for generating NTSC and PAL formatted video in a computer system A system and method for generating NTSC and PAL formatted composite video signals in a computer. Digital pixel data may be processed by software to form component video pixel data, which may include luminance and chrominance components. A chrominance look... | 09/22/1998 |
| 5805173 | System and method for capturing and transferring selected portions of a video stream in a computer system Aspects of the present invention provide a system for selectively processing a video signal in accordance with instructions from application software. The system contains a video decoder for converting an analog video signal to digital video data, and a c... | 09/08/1998 |
| 5790110 | System and method for generating video in a computer system A system and method for generating composite video signals in a computer. Digital pixel data may be processed by software to form component video pixel data, which may include luminance and chrominance components. A chrominance look-up table is provided i... | 08/04/1998 |
| 5789972 | Regulated reference voltage generator having feedback to provide a stable voltage An inverter receives an energizing voltage with a particular magnitude (e.g. 1.5 V) at a first terminal and produces the voltage at a second terminal. The received and produced voltages are differentially introduced to a stage which produces a single-ende... | 08/04/1998 |
| 5781132 | Error correcting decoder The magnitudes of an input voltage and individual ones of progressive fractions of a reference voltage are compared to produce first and second output voltages. Each of the elements in a first logical network receives the first output voltage from an indi... | 07/14/1998 |
| 5778055 | System for, and method of, transmitting and receiving through telephone lines signals representing data Analog signals representing individual digital values (&#b1;1, &#b1;3) pass through a telephone line to a receiver. These signals may be first provided in a pseudo random sequence. A linear echo canceller and a first adder eliminate, to an extent, echo si... | 07/07/1998 |
| 5777601 | System and method for generating video in a computer system A system and method for generating composite video signals in a computer. Digital pixel data may be processed by software to form component video pixel data, which may include luminance and chrominance components. A chrominance look-up table is provided i... | 07/07/1998 |
| 5768275 | Controller for ATM segmentation and reassembly A header and a payload in a cell are separated for transfer between a cell interface and a host memory. The header is transferred to a control memory. For transfer to the host memory, the control memory initially provides a host-memory region address and ... | 06/16/1998 |
| 5764074 | System for, and method of, minimizing noise in an integrated circuit chip The noise from the effects of currents through distributed capacitances between electrical circuitry on an integrated circuit chip and the chip substrate is minimized, especially for analog circuitry mixed on the chip with digital circuitry. The invention... | 06/09/1998 |
| 5761208 | Expansible high speed digital multiplexer A multiplexer, preferably on an integrated circuit chip, receives a plurality of buses each having a plurality of lines responsive to binary indications and passes the binary indications in the lines of a particular one of the buses. The multiplexer inclu... | 06/02/1998 |
| 5732279 | System and method for command processing or emulation in a computer system using interrupts, such as emulation of DMA commands using burst mode data transfer for sound or the like A system and method for providing sound in a computer are disclosed. An audio module for controlling digitized sound I/O is included in a media stream controller. The media stream controller may also coordinate graphics and video which allows multiple med... | 03/24/1998 |
| 5731744 | Voltage controlled oscillator An apparatus and a method are provided to obtain oscillations from a crystal at a particular frequency by introducing real and imaginary components of voltage to the crystal. The imaginary component of voltage is different from the real component of volta... | 03/24/1998 |
| 5717904 | Apparatus and methods for automatically controlling block writes A system for processing a stream of data and automatically selecting a portion or all of the data stream for block writing to a memory. The memory is capable of storing data in response to a block write command and a normal write command. The system conta... | 02/10/1998 |
| 5715437 | System for, and method of, processing in hardware commands received from software without polling of the hardware by the software A CPU introduces software commands to a first limited capacity memory (e.g. FIFO), on an integrated circuit chip. Data (e.g. graphics) from a first portion of a second memory (off chip) is processed in accordance with such commands. A second portion (e.g.... | 02/03/1998 |
| 5640332 | Multimedia graphics system Words of different types of digital information, including standard interframe video (SIF), graphics, television and audio are transferred preferably in packets between a controller, storage memory and shift registers (e.g. FIFO's) individually associated... | 06/17/1997 |
| 5640162 | Digital-to-analog converter with binary coded inputs to produce a plurality of outputs in the form of thermometer code Binary bits of least binary significance are converted to a corresponding analog output. Binary bits of increased binary significance are converted to a first plurality of thermometer outputs. A plurality of switching assemblies, each preferably recursive... | 06/17/1997 |
| 5638131 | Method to synchronize video modulation using a constant time base Successive pixels representing video data in successive lines in a raster scan are buffered. Each of the lines has a sync pulse defining the line beginning. A phase adjustment is determined between the sync pulse, preferably at a particular level in the s... | 06/10/1997 |
| 5631593 | Adjustable delay line A plurality of binary signals each having first and second logic levels respectively representing a binary "1" and a binary "0" and each indicating a binary digit of an individual binary significance cumulatively represent an adjustable delay to be provid... | 05/20/1997 |
| 5627396 | Micromachined relay and method of forming the relay A bridging member extending across a cavity in a semiconductor substrate (e.g. signal crystal silicon) has successive layers--a masking layer, an electrically conductive layer (e.g. polysilicon) and an insulating layer (e.g. SiO2). A first elec... | 05/06/1997 |
| 5627885 | System for, and method of, transmitting and receiving through telephone lines signals representing data Analog signals representing individual digital values (&#b1;1, &#b1;3) pass through a telephone line to a receiver. These signals may be first provided in a pseudo random sequence. A linear echo canceller and a first adder eliminate, to an extent, echo si... | 05/06/1997 |
| 5620933 | Micromachined relay and method of forming the relay A bridging member extending across a cavity in a semiconductor substrate (e.g. single crystal silicon) has successive layers--a masking layer, an electrically conductive layer (e.g. polysilicon) and an insulating layer (e.g. SiO2). A first elec... | 04/15/1997 |
| 5602495 | Apparatus for providing an output voltage with substantially identical rising and falling characteristics An inverter receives an energizing voltage with a particular magnitude (e.g. 1.5 V) at a first terminal and produces the voltage at a second terminal. The received and produced voltages are differentially introduced to a stage which produces a single-ende... | 02/11/1997 |
| 5596284 | System for, and method of, minimizing noise in an integrated circuit chip The noise from the effects of currents through distributed capacitances between electrical circuitry on an integrated circuit chip and the chip substrate is minimized, especially for analog circuitry mixed on the chip with digital circuitry. The invention... | 01/21/1997 |
| 5554950 | Delay line providing an adjustable delay in response to binary input signals A plurality of binary signals each having first and second logic levels respectively representing a binary "1" and a binary "0" and each indicating a binary digit of an individual binary significance cumulatively represent an adjustable delay to be provid... | 09/10/1996 |
| 5541598 | Current cell for converting a binary value to an analog value A digital value represented by binary signals is converted to a corresponding analog value by three (3) current cells, preferably C-MOS p-type, in a digital-to-analog converter (DAC). The three (3) transistors, preferably disposed on an integrated circuit... | 07/30/1996 |
| 5542041 | Apparatus for, and methods of, providing a universal format of pixels and for scaling fields in the pixels Raster display memories are often arranged to output groups of pixels in progressive blocks, each having a plurality of pixels and each pixel having a plurality of fields. The fields in each pixel may provide color, overlay and cursor information for an i... | 07/30/1996 |
| 5521539 | Delay line providing an adjustable delay First and second complementary input voltages control current flow through first and second switches (e.g. semiconductor devices) each respectively connected in first and second control circuits with a first constant current source. When the input voltage... | 05/28/1996 |
| 5500892 | Echo canceller Analog signals representing individual digital values (+3, +1, -1, -3) of data pass through a telephone line to a receiver. These signals may first be provided in a pseudo random sequence. A linear echo canceller and a first adder at the receiver simultan... | 03/19/1996 |
| 5486778 | Input buffer for translating TTL levels to CMOS levels An inverter receives an energizing voltage with a particular magnitude (e.g. 1.5 V) at a first terminal and produces the voltage at a second terminal. The received and produced voltages are differentially introduced to a stage which produces a single-ende... | 01/23/1996 |
| 5479042 | Micromachined relay and method of forming the relay A bridging member extending across a cavity in a semiconductor substrate (e.g. single crystal silicon) has successive layers--a masking layer, an electrically conductive layer (e.g. polysilicon) and an insulating layer (e.g. SiO2). A first elec... | 12/26/1995 |
| 5406306 | System for, and method of displaying information from a graphics memory and a video memory on a display monitor A display memory respectively stores, in first and second portions, digital graphics data for display in a video monitor and digital video data for display in a window in the monitor. The digital video data is transferred from the display memory to a shif... | 04/11/1995 |
| 5406285 | Digital-to-analog converter A system on an integrated circuit chip for providing a digital-to-analog conversion includes a plurality of output members each providing a particular current when energized. These members may be disposed on the chip in a pair of spaced columns. First con... | 04/11/1995 |
| 5406219 | Differential-to-single-ended converter First and second transistors respectively receive differential input signals each having first and second logic levels and respectively produce resultant currents dependent upon the levels of the input signals. The transistors may be CMOS transistors of t... | 04/11/1995 |
| 5404173 | Method to synchronize video modulation using a constant time base Successive pixels representing video data in successive lines in a raster scan are buffered. Each of the lines has a sync pulse defining the line beginning. A phase adjustment is determined between the sync pulse, preferably at a particular level in the s... | 04/04/1995 |
| 5400056 | Apparatus for and method of processing and converting binary information to corresponding analog signals In first and second modes, successive pairs of bytes, each with a suitable number (e.g. 8) of binary indications, are respectively processed in each clock cycle or clock half cycle to provide a true color. In these modes, the successive pairs of bytes may... | 03/21/1995 |
| 5379077 | System for and method of, operating upon NTSC and PAL signals A system converts PAL and NTSC pixel clock signals to signals (in a studio, digital or square pixel format) at a sub-carrier frequency individual to the PAL and NTSC formats. The system includes a first register for providing a particular increase in the ... | 01/03/1995 |
