Assignee: BTR, Inc.

Location: Reno, NV
No. of patents: 19

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Number	Title	Issue Date
7142012	Architecture and interconnect scheme for programmable logic circuits An architecture having a distributed and replicated hierarchical interconnect scheme for field programmable gate arrays (FPGAs). The FPGA is composed of a number of cells that perform logical functions on input signals. A set of block connectors are used to provide ...	11/28/2006
7126375	Floor plan for scalable multiple level tab oriented interconnect architecture A multiple level routing architecture for a programmable logic device having logical blocks, each logical block comprising a plurality of cells, with a first level routing resources coupling the cells of logical blocks. A second level routing resources coupling the ...	10/24/2006
7078933	Architecture and interconnect scheme for programmable logic circuits An architecture and distributed hierarchical interconnect scheme for field programmable gate arrays (FPGAs). The FPGA is comprised of a number of cells that perform logical functions on input signals. A set of block connectors are used to provide connectability betw...	07/18/2006
7017136	Architecture and interconnect scheme for programmable logic circuits An architecture of hierarchical interconnect scheme for field programmable gate arrays (FPGAs). A first layer of routing network lines is used to provide connections amongst sets of block connectors where block connectors are used to provide connectability between l...	03/21/2006
7009422	Floor plan for scalable multiple level tab oriented interconnect architecture A programmable logic device which incorporates an innovative routing hierarchy consisting of the multiple levels of routing lines, connector tab networks and turn matrices, enables an innovative, space saving floor plan to be utilized in an integrated circuit implem...	03/07/2006
6989688	Architecture and interconnect scheme for programmable logic circuits An architecture and distributed hierarchical interconnect scheme for field programmable gate arrays (FPGAs). The FPGA is comprised of a number of cells that perform logical functions on input signals. A set of block connectors are used to provide connectability betw...	01/24/2006
6703861	Architecture and interconnect scheme for programmable logic circuits An architecture and distributed hierarchical interconnect scheme for field programmable gate arrays (FPGAs). The FPGA is comprised of a number of cells which perform logical functions on input signals. Programmable intraconnections provide connectability ...	03/09/2004
6597196	Architecture and interconnect scheme for programmable logic circuits An architecture and distributed hierarchical interconnect scheme for field programmable gate arrays (FPGAs). The FPGA is comprised of a number of cells that perform logical functions on input signals. A set of block connectors are used to provide connecta...	07/22/2003
6507217	Architecture and interconnect scheme for programmable logic circuits An architecture and distributed hierarchical interconnect scheme for field programmable gate arrays (FPGAs). The FPGA is comprised of a number of cells which perform logical functions on input signals. Programmable intraconnections provide connectability ...	01/14/2003
6462578	Architecture and interconnect scheme for programmable logic circuits An architecture and distributed hierarchical interconnect scheme for field programmable gate arrays (FPGAs). The FPGA is comprised of a number of cells which perform logical functions on input signals. Programmable intraconnections provide connectability ...	10/08/2002
6433580	Architecture and interconnect scheme for programmable logic circuits An architecture and distributed hierarchical interconnect scheme for field programmable gate arrays (FPGAs). The FPGA is comprised of a number of cells which perform logical functions on input signals. Programmable intraconnections provide connectability ...	08/13/2002
6417690	Floor plan for scalable multiple level tab oriented interconnect architecture A programmable logic device which incorporates an innovative routing hierarchy consisting of the multiple levels of routing lines, connector tab networks and turn matrices, enables an innovative, space saving floor plan to be utilized in an integrated cir...	07/09/2002
6300793	Scalable multiple level tab oriented interconnect architecture An improved field programmable gate array (FPGA) is provided which includes tab network connectors for interfacing groups of configurable function generators with lower levels of interconnect and for interfacing lower levels of interconnect with higher le...	10/09/2001
6088526	Scalable multiple level tab oriented interconnect architecture An improved field programmable gate array (FPGA) is provided which includes tab network connectors for interfacing groups of configurable function generators with lower levels of interconnect and for interfacing lower levels of interconnect with higher le...	07/11/2000
6051991	Architecture and interconnect scheme for programmable logic circuits An architecture and distributed hierarchical interconnect scheme for field programmable gate arrays (FPGAs). The FPGA is comprised of a number of cells which perform logical functions on input signals. Programmable intraconnections provide connectability ...	04/18/2000
5850564	Scalable multiple level tab oriented interconnect architecture A programmable logic device which incorporates an innovative routing hierarchy consisting of the multiple levels of routing lines, connector tab networks and turn matrices, enables an innovative, space saving floor plan to be utilized in an integrated cir...	12/15/1998
5640327	Apparatus and method for partitioning resources for interconnections An apparatus and method for determining how to interconnect a plurality of components of a system, given a limited number of interconnect resources available to a device. First, it is determined whether the system meets the capacity constraints of the dev...	06/17/1997
5640344	Programmable non-volatile bidirectional switch for programmable logic A bidirectional passgate switch for connecting two conductors utilizes technology such as electrically erasable programmable read only memory (EEPROM). The switch includes two EEPROM components wherein the floating gates of the components are shared. In o...	06/17/1997
5457410	Architecture and interconnect scheme for programmable logic circuits An architecture and distributed hierarchical interconnect scheme for field programmable gate arrays (FPGAs). The FPGA is comprised of a number of cells which perform logical functions on input signals. Programmable intraconnections provide connectability ...	10/10/1995

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Assignee: BTR, Inc.