Assignee: Azul Systems, Inc.

Location: Mountain View, CA
No. of patents: 31

Number	Title	Issue Date
7865701	Concurrent atomic execution Executing a set one or more instructions atomically is disclosed. Executing includes saving a set of one or more register states in a software data structure, speculatively executing the set of instructions, and restoring the state of one or more registers when an a...	01/04/2011
7844862	Detecting software race conditions Detecting a race condition is disclosed. An indication of a store operation to a memory address is received. An identifier of the memory address is stored. The identifier is used to detect an occurrence of a memory operation that is not associated with a previous or...	11/30/2010
7840785	Transparent concurrent atomic execution Executing a block of code is disclosed. Executing includes receiving an indication that the block of code is to be executed using a synchronization mechanism and speculatively executing the block of code on a virtual machine. The block of code may include applicatio...	11/23/2010
7836280	Dynamic concurrent atomic execution Executing a set of one or more instructions atomically is disclosed. Executing includes determining whether speculatively executing the instructions is advised based at least in part on dynamic information associated with synchronization data and speculatively execu...	11/16/2010
7742398	Information redirection A technique is disclosed for redirecting information in a segmented virtual machine. The technique includes sending information to a shell VM and redirecting the information to bypass the shell VM. A technique for evaluating whether to redirect information may inclu...	06/22/2010
7689782	Processor instruction used to determine whether to perform a memory-related trap An instruction used by a processor in a determination of whether to perform a trap is disclosed. The instruction includes a first set of one or more bits identifying the instruction, and a second set of one or more bits associated with a first address value used in ...	03/30/2010
7669202	Resource management A technique for executing a segmented virtual machine (VM) is disclosed. A plurality of core VM's are implemented in a common core space. Each core VM is associated with a shell VM. Resources of the core space are allocated among the core VM's. A core VM is associat...	02/23/2010
7647458	Garbage collection A computer system includes a processor; and a memory coupled to the processor, configured to provide the processor with a plurality of instructions including a garbage collection barrier instruction and a subsequent instruction that immediately follows the garbage c...	01/12/2010
7620953	System and method for allocating resources of a core space among a plurality of core virtual machines A technique for executing a segmented virtual machine (VM) is disclosed. A plurality of core VM's is implemented in a plurality of core spaces. Each core VM is associated with one of a plurality of shell VM's. Resources of the core spaces are allocated among the cor...	11/17/2009
7577801	Array access Accessing memory in an array includes performing a first instruction, including by determining whether an index used by the first instruction is within a valid range and in the event that the index is within a valid range, determining a memory address related to an ...	08/18/2009
7565507	Cooperative memory management allowing program request and release memory as needed A computer system includes a memory and a processor coupled with the memory, configured to assign to each of a plurality of processes a corresponding amount of committed memory from a memory pool, the memory pool including committed memory and uncommitted memory; an...	07/21/2009
7552302	Ordering operation Executing an ordering operation is disclosed. A store operation associated with storing a value into a portion of a memory is initiated. An ordering operation to ensure that the store operation, but not necessarily all store operations, are completed is executed.	06/23/2009
7483824	Self-checking test generator for partially-modeled processors by propagating fuzzy states A self-checking test generator program creates a self-checking test program that can test a device under test (DUT). The self-checking test generator selects instructions for a test. Selected instructions are executed on a software DUT model to generate results that...	01/27/2009
7480908	Segmented virtual machine transport mechanism Providing data to an application running on a segmented virtual machine (VM) is disclosed. Providing data includes opening an interface between the segmented VM and an external data source, transferring data from the external data source to an interface buffer, tran...	01/20/2009
7469324	System and method for concurrent compacting self pacing garbage collection using loaded value and access barriers A method, system, and computer program product for managing a heap of memory allocated to a program being executed on a data processing system is disclosed. A limited amount of memory is allocated to a program being executed by a mutator on a data processing system....	12/23/2008
7437597	Write-back cache with different ECC codings for clean and dirty lines with refetching of uncorrectable clean lines A write-back cache has error-correction code (ECC) fields storing ECC bits for cache lines. Clean cache lines are re-fetched from memory when an ECC error is detected. Dirty cache lines are corrected using the ECC bits or signal an uncorrectable error. The type of E...	10/14/2008
7401202	Memory addressing Addressing memory includes receiving a first operand to a memory addressing operator, receiving a second operand to the memory addressing operator, performing sign extension on the first operand to provide a sign-extended operand, shifting the sign-extended operand ...	07/15/2008
7401178	Expanded memory space in environments including virtual machines Accessing data comprises executing a set of computer instructions in a first environment, wherein the first environment has limited addressing capability to address memory up to a size limit, specifying a set of data in a memory space of a second environment, wherei...	07/15/2008
7398449	Encoding 64-bit data nibble error correct and cyclic-redundancy code (CRC) address error detect for use on a 76-bit memory module A memory system provides data error detection and correction and address error detection. A cyclical-redundancy-check (CRC) code generates address check bits. A 32-bit address is compressed to 6 address check bits using the CRC code. The 6 address check bits are con...	07/08/2008
7376800	Speculative multiaddress atomicity A technique for performing a plurality of operations in a shared memory system having a plurality of addresses is disclosed. The technique includes entering into a speculative mode, speculatively performing each of the plurality of operations on addresses in the sha...	05/20/2008
7366847	Distributed cache coherence at scalable requestor filter pipes that accumulate invalidation acknowledgements from other requestor filter pipes using ordering messages from central snoop tag A multi-processor, multi-cache system has filter pipes that store entries for request messages sent to a central coherency controller. The central coherency controller orders requests from filter pipes using coherency rules but does not track completion of invalidat...	04/29/2008
7337339	Multi-level power monitoring, filtering and throttling at local blocks and globally Power management for a multi-processor chip includes a centralized global power manager that monitors global power for the whole chip, and local power managers. Local power managers manage power for local blocks such as processor cores, caches, and memory controller...	02/26/2008
7332929	Wide-scan on-chip logic analyzer with global trigger and interleaved SRAM capture buffers A system chip has many local blocks including processor cores, caches, and memory controllers. Each local block has a local sample-select mux that is controlled by a local selection control register. The mux selects from among hundreds of internal sample nodes in th...	02/19/2008
7278005	Cooperative memory management A method for managing memory in some embodiments comprises maintaining a memory pool, and specifying an amount of memory required for allocation. In some embodiments, the method also comprises requesting a process to release memory into the memory pool. In some embo...	10/02/2007
7263642	Testing replicated sub-systems in a yield-enhancing chip-test environment using on-chip compare to expected results for parallel scan chains testing critical and repairable sections of each sub-system A multi-processor chip has several processor cores that are simultaneously tested in parallel. The processor cores each have identical scan chains that produce identical test results absent defects. Expected test data is scanned from an external tester onto the chip...	08/28/2007
7257685	Memory management Improving performance of a computer program is disclosed. A first set of escape data is gathered. A first compiled program is provided using the first set of escape data. A second set of escape data is gathered based on the first compiled program. A second compiled ...	08/14/2007
7248587	Error recovery of variable-length packets without sequence numbers or special symbols used for synchronizing transmit retry-buffer pointer Variable-length packets transmitted over a serial link do not have packet-start fields or unique symbols to mark the beginning of each packet. Instead, a length field indicates the packet's length, allowing the end of the packet to be located. Packets also do not ha...	07/24/2007
7225300	Duplicate snoop tags partitioned across multiple processor/cache chips in a multi-processor system Several cluster chips and a shared main memory are connected by interconnect buses. Each cluster chip has multiple processors using multiple level-2 local caches, two memory controllers and two snoop tag partitions. The interconnect buses connect all local caches to...	05/29/2007
7203890	Address error detection by merging a polynomial-based CRC code of address bits with two nibbles of data or data ECC bits A memory system provides data error detection and correction and address error detection. A Single-byte Error-Correcting/Double-byte Error-Detecting (SbEC/DbED) code with the byte being a 4-bit nibble is used to detect up to 8-bit errors and correct data errors of 4...	04/10/2007
7117318	Memory management A technique for managing an object in memory is disclosed. The technique comprises: assigning the object to an assigned frame wherein the object can be released when the assigned frame is released; detecting an attempt to place a reference to the object in an older ...	10/03/2006
7053470	Multi-chip package having repairable embedded memories on a system chip with an EEPROM chip storing repair information A die with embedded memory is packaged together in a same dual-chip package with an EEPROM die. Defects in the embedded memory can be repaired using redundant rows or columns. A built-in self-test (BIST) controller locates defects and a repair image is generated. Th...	05/30/2006

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Assignee: Azul Systems, Inc.