Assignee: Arm Limited

Location: Cambridge, GB
No. of patents: 208

Number	Title	Issue Date
8185812	Single event upset error detection within an integrated circuit An integrated circuit 2 includes logic circuitry 10 and sequential storage elements 8. Both the logic circuit 10 and sequential storage elements 8 can be subject to particle strikes giving rise to single event upset errors. These s...	05/22/2012
8185791	Providing tuning limits for operational parameters in data processing apparatus Tuning limits are set for operational parameters in a processing stage within a data processing apparatus for processing a signal and outputting it at an output time. If a signal output between the output time and a predetermined time later does not have a stable va...	05/22/2012
8185786	Error recovery within processing stages of an integrated circuit An integrated circuit includes a plurality of processing stages each including processing logic, a non-delayed signal-capture element, a delayed signal-capture element and a comparator. The non-delayed signal-capture element captures an output from the processing lo...	05/22/2012
8185724	Monitoring values of signals within an integrated circuit An integrated circuit, and method of reviewing values of one or more signals occurring within that integrated circuit, are provided. The integrated circuit comprises processing logic for executing a program, and monitoring logic for reviewing values of one or more s...	05/22/2012
8180980	Device emulation support within a host data processing apparatus A data processing apparatus 12 is provided with a memory management unit 24 which triggers memory aborts. When a memory abort occurs, data characterizing the memory abort is written to a fault status register 28 (memory-abort register). The data...	05/15/2012
8180620	Apparatus and method for performing hardware and software co-verification testing Verification tests perform hardware and software co-verification on a system under verification. Each signal interface controller coupled to the system performs a test action transferring at least one of stimulus signals and response signals between a corresponding ...	05/15/2012
8176366	Trace synchronization A data processing apparatus having one or more trace data sources. At least one of said trace data sources includes a trace data generator responsive to activity in monitored circuitry to generate trace data representing said activity. A synchronization marker gener...	05/08/2012
8176262	Handling of memory access requests to shared memory in a data processing apparatus A data processing apparatus and method has a plurality of processing units, at least one of which is configured to be switchable between an active power state and a dormant power state and the units share a memory, and at least one local storage unit is configured t...	05/08/2012
8171386	Single event upset error detection within sequential storage circuitry of an integrated circuit Sequential storage circuitry for a integrated circuit is provided, comprising a first storage element, a second storage element and an additional storage element. The first storage element stores, during a first phase of a clock signal, a first indication of an inpu...	05/01/2012
8171311	Transferring data values via a data bus or storing data values using a selectable representation Data values being stored and transferred within a data processing system 8 have a selectable representation, such as true and complement, as indicated by an accompanying representation specifying bit. This assists in obscuring the operation and the power sign...	05/01/2012
8171191	Bus interconnect device and a data processing apparatus including such a bus interconnect device A bus interconnect device is provided comprising a parallel plate waveguide for coupling together a plurality of devices. This provides an efficient and flexible approach for providing interconnect functionality within a data processing apparatus. ...	05/01/2012
8164964	Boosting voltage levels applied to an access control line when accessing storage cells in a memory A semiconductor memory storage device is disclosed, the memory comprises: a plurality of storage cells for storing data; at least two access control lines each for controlling access to a respective at least one of the plurality of storage cells; at least two access...	04/24/2012
8161367	Correction of single event upset error within sequential storage circuitry of an integrated circuit Sequential storage circuitry includes first and second storage elements storing first and second indications of input data values received by the circuitry during first and second phases of a clock signal. Error detection circuitry detects a single event upset error...	04/17/2012
8160861	System and method for modelling a hardware component of a data processing apparatus The system comprises a component model for modelling aspects of the hardware component, and feature extraction logic for extending the component model to cause the component model, when executing, to output one or more features identifying execution behavior of the ...	04/17/2012
8159491	Apparatus and method for tracing activities of a shader program executed on shader circuitry of a data processing apparatus A data processing apparatus and method are provided for tracing activities of a shader program executed on shader circuitry of a data processing apparatus. The data processing apparatus comprises shader circuitry which is responsive to input data for a pixel to exec...	04/17/2012
8154353	Operating parameter monitor for an integrated circuit An integrated circuit 2 is provided with one or more monitoring circuits 14, 16, 18, 20 in the form of ring oscillators 22. These ring oscillators 22 include a plurality of tri-state inverters 24, 26, 28 containing a current-limiti...	04/10/2012
8151126	Controlling power consumption in a data processing apparatus A data processing apparatus, bus logic and method are provided for controlling power consumption within a data processing apparatus. The data processing apparatus has a plurality of logic elements, at least one of the logic elements being an initiator logic element ...	04/03/2012
8151055	Cache accessing using a micro TAG A data processing apparatus includes a data processor, and a data store for storing a plurality of identifiers identifying a cache way in which a corresponding value from a set associative cache is stored. The plurality of identifiers corresponding to a plurality of...	04/03/2012
8145960	Storage of data in data stores having some faulty storage locations Data storage control circuitry for controlling storage and retrieval of data in a data store in which data is stored in data blocks. A group data store stores data by grouping together blocks that have at least one faulty bit into groups of at least two blocks. For ...	03/27/2012
8145958	Integrated circuit and method for testing memory on the integrated circuit An integrated circuit and method for testing memory on the integrated circuit are provided. The integrated circuit has processing logic for performing data processing operations on data, and a plurality of memory units for storing data for access by the processing l...	03/27/2012
8145844	Memory controller with write data cache and read data cache A memory controller includes a write data cache, a read data cache and coherency circuitry. The coherency circuitry manages coherency of data between the write data cache, the read data cache and data stored within a main memory when servicing read requests and writ...	03/27/2012
8144167	Monitoring graphics processing A graphics processing apparatus is provided with rendering circuitry which separately renders different areas of a frame of pixel values. Monitoring circuitry coupled to the rendering circuitry captures for each area rendered one or more parameters and stores these ...	03/27/2012
8140820	Data processing apparatus and method for handling address translation for access requests issued by processing circuitry A data processing apparatus has address translation circuitry which is responsive to an access request specifying a virtual address, to perform a multi-stage address translation process to produce, via at least one intermediate address, a physical address in memory ...	03/20/2012
8136072	Standard cell placement A method of generating a layout of an integrated circuit is provided, the method comprising the steps of: providing functional data representing circuit elements and connections between the circuit elements, providing a cell library defining a plurality of standard ...	03/13/2012
8134824	Decoupling capacitors A decoupling capacitor is disclosed that has an n-type portion and a p-type portion in a semiconductor. The decoupling capacitor is formed of an NFET transistor and a PFET transistor, the PFET transistor being substantially formed in the n-type portion and the NFET ...	03/13/2012
RE43248	Interoperability with multiple instruction sets Data processing apparatus comprising: a processor core having means for executing successive program instruction words of a predetermined plurality of instruction sets; a data memory for storing program instruction words to be executed; a program counter register fo...	03/13/2012
8131942	Control data modification within a cache memory A data processing system is provided with at least one processor 4, 6, a main memory 18 and a cache memory 14. Cache data within the cache memory 14 has validity data V and control data associated therewith. The control data controls acce...	03/06/2012
8131901	Interrupt control for virtual processing apparatus A data processing system supporting one or more virtual processing apparatuses is provided with external interrupt interface hardware 26 and virtual interface hardware 28. Hypervisor software responds to an interrupt received by the external interrupt ...	03/06/2012
8122232	Self programming slave device controller A self programming slave device controller is described which comprises interface circuitry and control circuitry. The interface circuitry is responsive to one or more configuration parameters to communicate data between the slave device controller and a slave devic...	02/21/2012
8116165	Memory with improved data reliability An integrated circuit is provided including at least one array of memory cells having a plurality of rows of memory cells and a plurality of columns of bit cells. Each column of the memory cells is coupled to one of a plurality of bit lines. Each row of the memory c...	02/14/2012
8112681	Method and apparatus for handling fuse data for repairing faulty elements within an IC The application discloses an integrated circuit comprising: circuitry; a fusebox for storing an array of data identifying faulty elements within said circuitry; at least one fusebox controller for repairing said faulty elements in said circuitry in response to data ...	02/07/2012
8112560	Controlling complex non-linear data transfers A direct memory access controller for controlling data transfer between a plurality of data sources and a plurality of data destinations is disclosed. The plurality of data sources and data destinations communicate with the direct memory access controller via a plur...	02/07/2012
8108730	Debugging a multiprocessor system that switches between a locked mode and a split mode A data processing system 2 is provided with multiple processors 4, 6 which can operate in either a split-mode in which each processor executes its own program flow or a locked-mode in which the processors execute the same program flow. Debug circuitry ...	01/31/2012
8108596	Memory controller address mapping scheme A data processing system is provided with a memory controller (130) converting memory addresses (170) into selecting signals (120) for a memory device (100). The mapping between memory addresses and selecting signals is provided by mappin...	01/31/2012
8103990	Characterising circuit cell performance variability in response to perturbations in manufacturing process parameters A technique for characterising variation in a performance parameter(s) of circuit cells within a circuit cell library with perturbations in manufacturing process parameters uses a statistical approach whereby the statistical distribution of performance parameter(s) ...	01/24/2012
8103922	Error detection in precharged logic An integrated circuit is provided with domino logic including a speculative node and a checker node. Precharged circuitry precharges both the speculative node and the checker node. Logic circuitry provides a discharge path for the speculative node and the checker no...	01/24/2012
8103918	Clock control during self-test of multi port memory A multiport memory is provided with multiple data access paths A, B, each having a respective independent clock signal CLKA, CLKB. During self test operation a duplicate clock enable signal DPCLKTESTEN is used to enable one of these clock signals CLKA, CLKB to be us...	01/24/2012
8099635	Techniques for generating a trace stream for a data processing apparatus A data processing apparatus and method are provided for generating a trace stream. The data processing apparatus comprises logic for producing data elements, and trace logic for producing a stream of trace elements representative of at least some of the data element...	01/17/2012
8099556	Cache miss detection in a data processing apparatus A data processing apparatus and method are provided for detecting cache misses. The data processing apparatus has processing logic for executing a plurality of program threads, and a cache for storing data values for access by the processing logic. When access to a ...	01/17/2012
8093938	Cascoded level shifter protection A cascoded level shifter for receiving an input signal in a low voltage range and for generating an output signal in a high voltage range is disclosed. The cascoded level shifter is subdivided into a first voltage section and a second voltage section, the first volt...	01/10/2012

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Assignee: Arm Limited