Bizarre Patents
Pillow with retractable umbrella
A pillow assembly having a supporting assembly and a retractable umbrella assembly that is easily transportable and allows a user to support his/her head while covering their face from sunlight.
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| Number | Title | Issue Date |
| 8156359 | Low-power idle mode for network transceiver Low-power idle mode for network transceivers. In one aspect, a method for reducing power consumption of a transceiver connected to a communication network includes entering a low-power idle mode, and in this mode, repeatedly turning off a transmitter of the transcei... | 04/10/2012 |
| 8098768 | Compensation of ethernet transmit baseline wander Compensation of transmit baseline wander in data transmission on a network. In one aspect, compensating for baseline wander includes receiving a signal to be transmitted by a transmitter, where the transmitter is operable with a higher-speed transmission standard re... | 01/17/2012 |
| 8020070 | Trapping set decoding for transmission frames Trapping set decoding for transmission frames is disclosed. In one aspect, a trapping set decoder includes a decoder that performs decoding operations on an encoded codeword in received data, and a detector coupled to the decoder for detecting the presence of any on... | 09/13/2011 |
| 7818649 | Efficient message passing scheme of iterative error correcting decoders A decoder and method for implementing an iterative error correcting decoder are provided for decoding a codeword consisting of a N-bit messages. In one implementation, the decoder includes a first set of nodes, and a second set of nodes, each having N bits of resolu... | 10/19/2010 |
| 7805642 | Low power iterative decoder using input data pipelining and voltage scaling A decoder architecture and method for processing codewords are provided. In one implementation, the decoder architecture includes an input buffer configured to receive and store one or more codewords to be processed, and a decoder configured to receive codewords one... | 09/28/2010 |
| 7797613 | Digital implementation of an enhanced minsum algorithm for error correction in data communications An iterative error correcting decoder is provided. In one implementation, the iterative error correcting decoder includes an equality constraint node and a parity check node, the parity check node. The parity check node includes parity logic configured to receive in... | 09/14/2010 |
| 7739558 | Method and apparatus for rectifying errors in the presence of known trapping sets in iterative decoders and expedited bit error rate testing A method and system for determining low error rate behavior of a device are provided. In one implementation, the method includes obtaining a dominant trapping set of a code, the dominant trapping set containing a plurality of variable nodes, and biasing bits associa... | 06/15/2010 |
| 7706434 | Method and apparatus for cancelling interference in a communication system Methods and systems for cancelling interference in an analog communication signal are provided. The method includes receiving an analog communication signal including interference caused by a deterministic interference source, generating a digital interference signa... | 04/27/2010 |
| 7675450 | Digital-to-analog converter (DAC) for high frequency and high resolution environments A digital-to-analog converter (DAC) configured to operate in high frequency and/or high resolution environments. The DAC has a segmented architecture comprising one or more least significant bit (LSB) thermometer sub-converters and one or more most significant bit (... | 03/09/2010 |
| 7669106 | Optimization of low density parity check (LDPC) building blocks using multi-input Gilbert cells Described are an iterative decoder and method for implementing an iterative decoder which can be used for error correction in data communications. In one implementation, the method includes implementing a first function including a first plurality of Gilbert cells, ... | 02/23/2010 |
| 7663412 | Method and apparatus for providing leakage current compensation in electrical circuits A circuit is provided that (in one implementation) includes a first transistor having a first drain terminal, first gate terminal, and a first source terminal. The first drain terminal is connected to the first gate terminal, the first source terminal is connected t... | 02/16/2010 |
| 7589567 | Compensation technique for current source channel-length modulation A circuit is provided that includes a current source, and a compensation circuit to generate a compensation current based on an output voltage of the current source. The circuit further includes a combiner to combine the compensation current with an output current o... | 09/15/2009 |
| 7583724 | Low-power mixed-mode echo/crosstalk cancellation in wireline communications A signal processing system includes an AGC and pre-echo cancellation system for receiving an analog signal, amplifying signal magnitude (over all frequencies) to a pre-determined level by AGC, and removing the immediate transmit pulse from this received signal by pr... | 09/01/2009 |
| 7577891 | Method and apparatus for extending decoding time in an iterative decoder using input codeword pipelining A decoder architecture and method for implementing a decoder are provided. In one implementation, the decoder architecture includes an input buffer configured to receive a plurality of codewords to be processed, and includes an iterative decoder configured to receiv... | 08/18/2009 |
| 7532048 | Multi-level variable-resistor line driver The line driver circuit is provided that includes a first pull-up variable resistor connected between a first power supply and the first output terminal, a second pull-up variable resistor connected between the first power supply and the second output terminal, a fi... | 05/12/2009 |
| 7221196 | Low-power low-voltage multi-level variable-resistor line driver A low-power multi-level pulse amplitude modulation (PAM) line driver using variable resistors is disclosed for transmitting digital data over controlled-impedance transmission lines. This invention discloses the design of a multi-level PAM driver for high-speed wire... | 05/22/2007 |
