Did You Know...
...that in the early 1940s GE engineer James Wright was charged with a task of utmost importance to the war effort: develop a cheap substitute for rubber that could be used to produce tires, gas masks and a whole host of military gear. Wright tackled the task diligently -- and wound up inventing Silly Putty.
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 6453344 | Multiprocessor servers with controlled numbered of CPUs A multiprocessor system having a total number of available CPUs partitioned into one or more smaller pools of CPUs called servers where the number of CPUs available to a server is reduced below the total number of available CPUs. Software licensing costs ... | 09/17/2002 |
| 6397216 | Ordering keys in a table using an ordering mask The present invention is a mask ordering method and apparatus which controls the way keys are compared. In its general form, the mask ordering method operates to order (with a less than, greater than or equal to comparison) two N-byte (for example, N=16) ... | 05/28/2002 |
| 6393411 | Device and method for authorized funds transfer A secure funds device for use with a computer system, such as a personal computer, for transferring funds, in response to a funds transfer request for amounts of funds from the computer system, to a funds receiver. One or more electronic cash devices stor... | 05/21/2002 |
| 6289457 | Value data system having containers for theft deterrent repositories A value data system for secure electronic storage, transfer and other processing of value data using repositories of security controlled devices. The value data system includes a repository container including one or more of the repositories and a contain... | 09/11/2001 |
| 6286089 | Coupling facility using dynamic address translation A system that employs virtual addressing for structures in a coupling facility. The system operates to share data among two or more processes that execute on central processing complexes. The central processing complexes each have an inter-system channel ... | 09/04/2001 |
| 6195750 | Method and apparatus for dynamic CPU reconfiguration in a system employing logical processors A multiprocessor system having a plurality of CPUs that can be dynamically reconfigured between online and offline without system shutdown. The multiprocessor system includes a dynamic reconfiguration subsystem for reconfiguration without shutdown. The dy... | 02/27/2001 |
| 6145066 | Computer system with transparent data migration between storage volumes A computer system includes a transparent data migration facility (TDNff) to accomplish automated movement of data (migration) from one location to another in the system. A data migration program includes a main module to control the start of a migration s... | 11/07/2000 |
| 5748976 | Mechanism for maintaining data coherency in a branch history instruction cache A system for maintaining the integrity of data stored in a branch prediction mechanism such as a branch target buffer (BTB). Upon encountering a branch instruction, a stream of target instructions is prefetched from cache memory even though the target ins... | 05/05/1998 |
| 5682535 | Operating system and data base using table access method with dynamic binding A system for program development and execution consisting of a high level programming language based on a four part rule organization, consisting of a rule definition, a list of conditions, a list of actions which are taken upon satisfaction of a correspo... | 10/28/1997 |
| 5651113 | Method and apparatus for indicating a time-out by generating a time stamp for an input/output (I/O) channel whenever the channel processes an instruction A channel time-out apparatus in a data processing system having a channel processor for controlling the allocation of a plurality of input/output channels. The channel time-out apparatus comprises a clock for generating time indications, an address genera... | 07/22/1997 |
| 5615327 | Apparatus and method for controlling the initiating of a synchronization protocol for synchronizing a plurality of processors in a multi-processor system A multiprocessor (MP) computer sytem which allows target CPU(s) to continue processing instructions while other target CPU(s) are processing instructions of emulation code to reach their end of a Domain Unit of Operation before synchronization. A two-leve... | 03/25/1997 |
| 5603008 | Computer system having cache memories with independently validated keys in the TLB A storage unit for a data processing system includes a cache data buffer, a cache tag, and a translation lookaside buffer (TLB). Storage keys are maintained in the TLB with a separate valid bit, which allows a valid translation to be stored upon completio... | 02/11/1997 |
| 5596752 | System for creating, editing, displaying, and executing rules-based programming language rules having action part subsets for both true and false evaluation of the conditional part A programmable computer which operates by executing rules, each including a rule name, and optionally: input parameters, a set of conditions, a set of actions associated with each condition, and a set of exception handlers. A condition is a logical expres... | 01/21/1997 |
| 5594899 | Operating system and data base having an access structure formed by a plurality of tables An object access system for retrieving objects in response to requests identifying requested objects, the system comprising an access structure consisting of a plurality of tables where each table is identified by a unique table identifier and has a plura... | 01/14/1997 |
| 5588134 | System for establishing priority among selected tasks based on location of tasks and sequence that the tasks were stored whereas task is always stored in location with the lowest available address In a system having a plurality of sources for generating tasks and a plurality of receivers for receiving said tasks wherein a plurality of said tasks for one or more said receivers may be generated at the same time by one or more of said sources, each sa... | 12/24/1996 |
| 5586329 | Programmable computer with automatic translation between source and object code with version control A computer which executes rules which are defined according to a language having a valid grammar. The computer comprises input means for receiving and temporarily storing a first source code representation of a rule; object code translation means for tran... | 12/17/1996 |
| 5586330 | Programmable computer with automatic translation between source and object code A method for manipulating a database of data and rules stored in a computer system where the computer operates in accordance with object-coded rules defined by a specified object code grammar. The computer including storage means for storing data and obje... | 12/17/1996 |
| 5584026 | Computer method for implementing a GET instruction A computer method for executing a GET instruction for retrieving the first record stored in a data base that meets the stated criteria and for issuing an exception when no such record is found.... | 12/10/1996 |
| 5581794 | Apparatus for generating a channel time-out signal after 16.38 milliseconds An apparatus and method for processing channel time-out for input/output channels in a data processing system. A counting device is provided which cycles through a count indicative, in a first part, of each of a plurality of channels in the data processin... | 12/03/1996 |
| 5574936 | Access control mechanism controlling access to and logical purging of access register translation lookaside buffer (ALB) in a computer system An access control apparatus in a computer system for controlling access to an ALB. A host ALBID register and a guest ALBID register is provided for storing a host and a guest ALB identifier (ALBID) and a host and a guest ALBID validity indicator. Control ... | 11/12/1996 |
| 5574393 | Apparatus and method for immediately stopping clocks A bypass means is provided for bypassing a system clock disabling signal around a conventional system clock disabling signal processing path to reduce the amount of delay between the occurrence of the disabling signal and a stopping of the system clock.... | 11/12/1996 |
| 5553285 | File system for a plurality of storage classes A file system for managing data files for access by a plurality of users of a data processing system that includes internal storage for buffering, external storage, and a file user interface by which the plurality of users request access to data files. A ... | 09/03/1996 |
| 5517668 | Distributed protocol framework A distributed computing system having a distributed protocol stack. In a system including one or more general purpose computers or other application processors for running applications, the distributed protocol stack off-loads communication or other I/O p... | 05/14/1996 |
| 5517514 | Parity checking system with reduced usage of I/O pins A data integrity system comprising a plurality of units connected together for the transfer of data between the units. Each said unit comprises data means for receiving data from one or more other units and/or transmitting data to one or more other units,... | 05/14/1996 |
| 5502819 | Clock distribution system for reducing clock skew between processors in a dual sided tightly coupled system A clock distribution system for reducing clock skew between tightly coupled central processing units in a multi-processor system. The multi-processor system includes (1) a configuration processor for generating a first configuration signal and a second co... | 03/26/1996 |
| 5491799 | Communication interface for uniform communication among hardware and software units of a computer system A SYStem COMmunication interface (SYSCOM) unit provides uniform communication between hardware and software units of a computer system. The computer units include Central Processing Units (CPU's), Input/Output Processors (IOP's), Service Processor (SVP), ... | 02/13/1996 |
| 5490255 | Expedited execution of pipelined command having self-ordering operand processing requirements A pipelined computer which process operand data through a sequence of D,A,T,B,X and W stages includes a sidetrack queue. Data which exits the B stage prematurely, before the X stage is ready to immediately process such data, is held over in the sidetrack ... | 02/06/1996 |
| 5490250 | Method and apparatus for transferring indication of control error into data path of data switcher The invention provides a method and apparatus for tagging a control error indication onto a data signal passing through a data router in a computer system.... | 02/06/1996 |
| 5488706 | Retry request system in a pipeline data processing system where each requesting unit preserves the order of requests An interface between a storage unit and a system control unit maintains a sequential processing when retrying linestores by providing a single piece of information that the linestore is a "first" in a series. An initial request flag accompanies linestore ... | 01/30/1996 |
| 5487166 | Computer with two-dimensional merge tournament sort using offset-value coding To perform a sort of N records, a two-dimensional tree structure is formed with a tree of subtrees, where each subtree is formed by a plurality of nodes organized in a binary tree. For each leaf node in the tree, there is an ancestor chain of nodes (from ... | 01/23/1996 |
| 5459872 | Software control of hardware interruptions In a computer system including an interrupt processor for interrupting a program being processed by the computer system, a sub-system for processing interrupt requests to the interrupt processor. The sub-system comprises hardware circuit for generating ha... | 10/17/1995 |
| 5457781 | System having main unit for shutting off clocks to memory upon completion of writing data into memory and information supervising unit to read the data The invention provides a method and apparatus for immediate control communications between supervising and main processor units. A method in accordance with the invention comprises the steps of: providing a communications memory means within a first clock... | 10/10/1995 |
| 5452309 | Apparatus and method for forcing hardware errors via scan An apparatus and method for forcing stuck-at and transient errors at sequential and combinational logic and signal lines in a large scale data processing system. Error forcing is achieved by including a scan-in gate with error input and address lines for ... | 09/19/1995 |
| 5444859 | Method and apparatus for tracing multiple errors in a computer system subsequent to the first occurence and prior to the stopping of the clock in response thereto An approach to error assessment in computer systems is based on storing important state information while the machine is operating in a trace memory for each cycle of the clock. The trace memory is then coupled through the scan interface or otherwise to t... | 08/22/1995 |
| 5426783 | System for processing eight bytes or less by the move, pack and unpack instruction of the ESA/390 instruction set A processing system comprising a first means for generating first signals indicating when the next instruction can begin processing where eight or less bytes are processed by the MOVE, PACK or UNPACK instruction, a second means for generating second signa... | 06/20/1995 |
| 5423025 | Error handling mechanism for a controller having a plurality of servers An error handling and reporting mechanism is capable of taking advantage of sophisticated error analysis performed after clocks have been stopped in response to an error detected in a controller. The controller provides services in a data processing syste... | 06/06/1995 |
| 5418794 | Error determination scan tree apparatus and method An error detection scan tree apparatus and method including a plurality of error detection devices in which an error signal generated by an error detection device is propagated from the detection device through the scan tree of minimalistic structure to a... | 05/23/1995 |
| 5410668 | Reconfigurable cache memory which can selectively inhibit access to damaged segments in the cache memory A cache memory system includes a buffer having a plurality of segments storing lines of data in addressable storage locations. A first access path is used for accessing the plurality of segments in parallel for access by the CPU, and a second access path ... | 04/25/1995 |
| 5408674 | System for checking the validity of two byte operation code by mapping two byte operation codes into control memory in order to reduce memory size A mapping system for mapping a plurality of two byte operation code series into a control store where in each two byte operation code the first byte identifies the series in which that two byte operation code is included and the second byte identifies tha... | 04/18/1995 |
| 5390323 | Microstore reference logging The invention provides a method and apparatus for logging all references to microstore addresses irrespective of the number of times that a same address is referenced and irrespective of the order in which addresses are referenced. It provides a log indic... | 02/14/1995 |
