Assignee: Amberwave Systems Corporation

Location: Salem, NH
No. of patents: 39

Number	Title	Issue Date
7638842	Lattice-mismatched semiconductor structures on insulators Monolithic lattice-mismatched semiconductor heterostructures are fabricated by bonding patterned substrates with alternative active-area materials formed thereon to a rigid dielectric platform and then removing the highly-defective interface areas along with the und...	12/29/2009
7626246	Solutions for integrated circuit integration of alternative active area materials Methods of forming areas of alternative material on crystalline semiconductor substrates, and structures formed thereby. Such areas of alternative material are suitable for use as active areas in MOSFETs or other electronic or opto-electronic devices. ...	12/01/2009
7615829	Elevated source and drain elements for strained-channel heterojuntion field-effect transistors A semiconductor structure having a surface layer disposed over a substrate, the surface layer including strained silicon. A contact layer is disposed over a portion of the surface layer, the contact layer including a metal-semiconductor alloy. A bottommost boundary ...	11/10/2009
7594967	Reduction of dislocation pile-up formation during relaxed lattice-mismatched epitaxy A semiconductor structure including a cap layer formed over a semiconductor substrate having a rough edge, which discourages formation of dislocation pile-up defects. ...	09/29/2009
7588994	Methods for forming strained-semiconductor-on-insulator device structures by mechanically inducing strain The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. ...	09/15/2009
7566606	Methods of fabricating semiconductor devices having strained dual channel layers A semiconductor structure includes a strain-inducing substrate layer having a germanium concentration of at least 10 atomic %. The semiconductor structure also includes a compressively strained layer on the strain-inducing substrate layer. The compressively strained...	07/28/2009
7541208	Methods for preserving strained semiconductor substrate layers during CMOS processing Oxidation methods, which avoid consuming undesirably large amounts of surface material in Si/SiGe heterostructure-based wafers, replace various intermediate CMOS thermal oxidation steps. First, by using oxide deposition methods, arbitrarily thick oxides may be forme...	06/02/2009
7504704	Shallow trench isolation process A structure including a transistor and a trench structure, with the trench structure inducing only a portion of the strain in a channel region of the transistor. ...	03/17/2009
7501351	Relaxed SiGe platform for high speed CMOS electronics and high speed analog circuits Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. ...	03/10/2009
7494881	Methods for selective placement of dislocation arrays Misfit dislocations are selectively placed in layers formed over substrates. Thicknesses of layers may be used to define distances between misfit dislocations and surfaces of layers formed over substrates, as well as placement of misfit dislocations and dislocation ...	02/24/2009
7465619	Methods of fabricating dual layer semiconductor devices A semiconductor-based device includes a channel layer, which includes a distal layer and a proximal layer in contact with the distal layer. The distal layer supports at least a portion of hole conduction for at least one p-channel component, and the proximal layer s...	12/16/2008
7439164	Methods of fabricating semiconductor structures having epitaxially grown source and drain elements Methods for fabricating facetless semiconductor structures using commercially available chemical vapor deposition systems are disclosed herein. A key aspect of the invention includes selectively depositing an epitaxial layer of at least one semiconductor material on...	10/21/2008
7420201	Strained-semiconductor-on-insulator device structures with elevated source/drain regions The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. ...	09/02/2008
7416909	Methods for preserving strained semiconductor substrate layers during CMOS processing Oxidation methods, which avoid consuming undesirably large amounts of surface material in Si/SiGe heterostructure-based wafers, replace various intermediate CMOS thermal oxidation steps. First, by using oxide deposition methods, arbitrarily thick oxides may be forme...	08/26/2008
7414259	Strained germanium-on-insulator device structures The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. ...	08/19/2008
7410861	Methods of forming dynamic random access memory trench capacitors DRAM trench capacitors formed by, inter alia, deposition of conductive material into a trench or doping the semiconductor region in which the trench is defined. ...	08/12/2008
7408214	Dynamic random access memory trench capacitors DRAM trench capacitors formed by, inter alia, deposition of conductive material into a trench or doping the semiconductor region in which the trench is defined. ...	08/05/2008
7393733	Methods of forming hybrid fin field-effect transistor structures Semiconductor-on-insulator structures facilitate the fabrication of devices, including MOSFETs that are at least partially depleted during operation and FinFETs including bilayer fins and/or crystalline oxide. ...	07/01/2008
7375385	Semiconductor heterostructures having reduced dislocation pile-ups Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading di...	05/20/2008
7368308	Methods of fabricating semiconductor heterostructures Dislocation pile-ups in compositionally graded semiconductor layers are reduced or eliminated, thereby leading to increased semiconductor device yield and manufacturability. This is accomplished by introducing a semiconductor layer having a plurality of threading di...	05/06/2008
7335545	Control of strain in device layers by prevention of relaxation The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. Strain in the strained semiconductors is controlled for improved device performance. ...	02/26/2008
7332417	Semiconductor structures with structural homogeneity Semiconductor structures are formed with semiconductor layers having reduced compositional variation. Top surfaces of the semiconductor layers are substantially haze-free. ...	02/19/2008
7326599	Gate material for semiconductor device fabrication In forming an electronic device, a semiconductor layer is pre-doped and a dopant distribution anneal is performed prior to gate definition. Alternatively, the gate is formed from a metal. Subsequently formed shallow sources and drains, therefore, are not affected by...	02/05/2008
7307273	Control of strain in device layers by selective relaxation The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. Strain in the strained semiconductors is controlled for improved device performance. ...	12/11/2007
7297612	Methods for forming strained-semiconductor-on-insulator device structures by use of cleave planes The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. ...	11/20/2007
7259388	Strained-semiconductor-on-insulator device structures The benefits of strained semiconductors are combined with silicon-on-insulator approaches to substrate and device fabrication. ...	08/21/2007
7259108	Methods for fabricating strained layers on semiconductor substrates Methods for fabricating multi-layer semiconductor structures including strained material layers using a minimum number of process tools and under conditions optimized for each layer. Certain regions of the strained material layers are kept free of impurities that ca...	08/21/2007
7256142	Relaxed SiGe platform for high speed CMOS electronics and high speed analog circuits Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. ...	08/14/2007
7217668	Gate technology for strained surface channel and strained buried channel MOSFET devices A method of fabricating a semiconductor device including providing a semiconductor heterostructure, the heterostructure having a relaxed Si1-xGex layer on a substrate, a strained channel layer on the relaxed Si1-xGex layer...	05/15/2007
7217603	Methods of forming reacted conductive gate electrodes A semiconductor device and a method for fabricating a semiconductor device involve a semiconductor layer that includes a first material and a second material. The first and second materials can be silicon and germanium. A contact of the device has a portion proximal...	05/15/2007
7208332	Methods for preserving strained semiconductor substrate layers during CMOS processing Oxidation methods, which avoid consuming undesirably large amounts of surface material in Si/SiGe heterostructure-based wafers, replace various intermediate CMOS thermal oxidation steps. First, by using oxide deposition methods, arbitrarily thick oxides may be forme...	04/24/2007
7202121	Methods for preserving strained semiconductor substrate layers during CMOS processing Oxidation methods, which avoid consuming undesirably large amounts of surface material in Si/SiGe heterostructure-based wafers, replace various intermediate CMOS thermal oxidation steps. First, by using oxide deposition methods, arbitrarily thick oxides may be forme...	04/10/2007
7122449	Methods of fabricating semiconductor structures having epitaxially grown source and drain elements Methods for fabricating facetless semiconductor structures using commercially available chemical vapor deposition systems are disclosed herein. A key aspect of the invention includes selectively depositing an epitaxial layer of at least one semiconductor material on...	10/17/2006
6960781	Shallow trench isolation process A structure including a transistor and a trench structure, with the trench structure inducing only a portion of the strain in a channel region of the transistor. ...	11/01/2005
6946371	Methods of fabricating semiconductor structures having epitaxially grown source and drain elements Methods for fabricating facetless semiconductor structures using commercially available chemical vapor deposition systems are disclosed herein. A key aspect of the invention includes selectively depositing an epitaxial layer of at least one semiconductor material on...	09/20/2005
6933518	RF circuits including transistors having strained material layers Circuits for processing radio frequency (“RF”) and microwave signals are fabricated using field effect transistors (“FETs”) that have one or more strained channel layers disposed on one or more planarized substrate layers. FETs having such a configuration ex...	08/23/2005
6900103	Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. ...	05/31/2005
6830976	Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits Structures and methods for fabricating high speed digital, analog, and combined digital/analog systems using planarized relaxed SiGe as the materials platform. The relaxed SiGe allows for a plethora of strained Si layers that possess enhanced electronic properties. ...	12/14/2004
6593191	Buried channel strained silicon FET using a supply layer created through ion implantation A method of fabricating a buried channel FET including providing a relaxed SiGe layer on a substrate, providing a channel layer on the relaxed SiGe layer, providing a SiGe cap layer on the channel layer, and ion implanting a dopant supply. The dopant supp...	07/15/2003

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Assignee: Amberwave Systems Corporation