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| Number | Title | Issue Date |
| 8185861 | Variable sized soft memory macros in structured cell arrays, and related methods The logic cells (HLEs) of a structured application-specific integrated circuit (structured ASIC) can be used to provide memory blocks of various sizes. Any one or more of several techniques may be employed to facilitate doing this for various user designs that may h... | 05/22/2012 |
| 8185854 | Method and apparatus for performing parallel slack computation within a shared netlist region A method for designing a system on a target device is disclosed. Domains and sub-domains in the system are identified. A sub-domain is divided into a plurality of chunks. Slacks for the chunks are computed in parallel. Other embodiments are described and claimed. | 05/22/2012 |
| 8185714 | Method and apparatus for strobe-based source-synchronous capture using a first-in-first-out unit A source-synchronous capture unit includes a data register unit to register data synchronized to a strobe or non-free running clock. The source synchronous capture unit also includes an asynchronous first-in-first-out (FIFO) unit to store the data from the data regi... | 05/22/2012 |
| 8184651 | PLD architecture optimized for 10G Ethernet physical layer solution An integrated circuit (e.g., a programmable integrated circuit such as a programmable microcontroller, a programmable logic device, etc.) includes programmable circuitry and 10 Gigabit Ethernet (10 GbE) transceiver circuitry. The programmable circuitry and the trans... | 05/22/2012 |
| 8183921 | Offset cancellation for continuous-time circuits One embodiment relates to a continuous-time circuit configured with an offset cancellation loop. The continuous-time circuit includes a multi-stage amplifier chain, including a first amplifier stage and a last amplifier stage, and an offset cancellation loop. The of... | 05/22/2012 |
| 8183883 | Integrated circuit reconfiguration techniques A memory configuration circuit is provided. The memory configuration circuit may be integrated into a programmable logic device (PLD) and as such, may be used to configure and reconfigure specific elements in the PLD. The memory configuration circuit includes a comp... | 05/22/2012 |
| 8181146 | Equivalence checker A method for performing equivalency checking between circuit designs is provided. The method includes partitioning the circuit designs into logic cones. The method includes comparing corresponding logic cones for equivalency. The comparing includes identifying const... | 05/15/2012 |
| 8181130 | Method for jitter reduction by shifting current consumption A method for jitter reduction in a path of an integrated circuit design is presented. The path is first analyzed to identify a combinatorial logic element bounded between a source element and a destination element. The arrival time of the input signal to the combina... | 05/15/2012 |
| 8176450 | Method and apparatus for parameterizing hardware description language code in a system level design environment A method for managing an electronic design automation tool includes importing a component. A graphical user interface is generated to allow a user to enter values for parameters of the component. Other embodiments are disclosed. ... | 05/08/2012 |
| 8176111 | Low latency floating-point divider An improved method and apparatus for performing floating-point division is disclosed. In a particular embodiment, fractional operands are pre-scaled and an estimate of a reciprocal of the pre-scaled fractional divisor is obtained from a lookup table using a portion ... | 05/08/2012 |
| 8175143 | Adaptive equalization using data level detection A method, and circuitry, for choosing the correct equalization curve in adaptive equalization uses a feedback loop in which the incoming high-speed serial data are digitized and deserialized for use in the remainder of the device, and also are used by an adaptive st... | 05/08/2012 |
| 8174294 | Configurable buffer circuits and methods A buffer circuit includes a current source circuit, first and second switch circuits that are coupled to the current source circuit, a first resistor coupled to the first switch circuit, a second resistor coupled to the second switch circuit, and a third switch circ... | 05/08/2012 |
| 8174284 | Repairable IO in an integrated circuit Methods and structures for implementing repairable input/output (IO) circuitry in an integrated circuit (IC) are disclosed. One embodiment of the present invention includes repairable IO circuitry along a right, left, or inner column of an IC. Another embodiment inc... | 05/08/2012 |
| 8171443 | Circuit design tools that support devices with real-time phase-locked loop reconfiguration capabilities Computer-aided-design tools are provided that support real-time phase-locked loop reconfiguration with a single design compilation. Each design compilation may involve operations such as logic synthesis and place and route operations. A circuit designer who is desig... | 05/01/2012 |
| 8171158 | Browser system and method A portable apparatus for viewing digital content received from a data communication network, includes: a non-volatile storage medium capable to store digital content received from a data communication network; a display communicatively coupled to the non-volatile st... | 05/01/2012 |
| 8170823 | Jitter estimation in phase-locked loops A phase-locked loop is characterized by analyzing phase noise in its output signal while known levels of input phase noise are provided. The resulting data provides intrinsic phase noise and gain of the phase-locked loop. These values provide a general relationship ... | 05/01/2012 |
| 8166447 | Power delivery network calculator tool for printed circuit board capacitors A method of calculating a system power distribution network impedance is presented. The impedance calculation calculates the impedance as separate elements of the printed circuit board (PCB). An approximation of the power and ground via inductance of the printed cir... | 04/24/2012 |
| 8166436 | Early logic mapper during FPGA synthesis Programming software defining an algorithm that provides improved power, area and frequency predictability of a logic design early in the synthesis flow process, prior to Technology Mapping, without degrading the power, speed or area of the design implementation for... | 04/24/2012 |
| 8166429 | Multi-layer distributed network Apparatuses and processes for distributing signals in an integrated circuit are disclosed. An embodiment to use a custom layer together with a base layer on an integrated circuit for testing the integrated circuit includes having a structured network on the base lay... | 04/24/2012 |
| 8166427 | Tracing and reporting registers removed during synthesis Circuits, methods, software, and apparatus that track the removal of, reasons for, and consequence of the removal of registers or other circuitry during the synthesis of electronic circuits. An exemplary embodiment of the present invention tracks the removal of regi... | 04/24/2012 |
| 8166237 | Configurable allocation of thread queue resources in an FPGA A programmable logic device includes a hard-logic portion that selectively aggregates bandwidth of data ports and maps logically and physically the transactions from these ports. The memory interface structure is a part of a hard-logic portion that includes random a... | 04/24/2012 |
| 8165191 | Multi-protocol channel-aggregated configurable transceiver in an integrated circuit Embodiments in the disclosure include a multi-protocol transceiver including a configurable arrangement of receive and/or transmit circuitry. An exemplary transceiver can be selectively configured to effectively transmit and/or receive data communications correspond... | 04/24/2012 |
| 8165033 | Method and apparatus for performing generalized processor sharing scheduling A scheduler includes a sorting unit that has n comparators to identify a smallest virtual finish time (VFT) value from 2n VFT entries. Each of the VFT entries may include a valid bit to indicate its validity. ... | 04/24/2012 |
| 8163642 | Package substrate with dual material build-up layers Multi-layered, organic build-up semiconductor package substrates have build-up layers with layers of both fibrous organic dielectric material and non-fibrous organic dielectric material. Non-fibrous dielectric material layers are positioned below the signal metal la... | 04/24/2012 |
| 8161469 | Method and apparatus for comparing programmable logic device configurations Compiled configuration files for different programmable logic devices that are intended to be functionally equivalent may be compared using multiple different comparisons to assure functional equivalence. The different comparisons include a fitter or resource report... | 04/17/2012 |
| 8161444 | Allocating hardware resources for high-level language code sequences Methods and apparatus are provided for implementing a programmable chip using a high-level language. Code sequences or subroutines provided in a high-level language are overloaded with information to specify the number of hardware resources such as logic elements or... | 04/17/2012 |
| 8161429 | Methods and apparatus for initializing serial links A serial communications protocol is provided that has optional link initialization features such as an optional automatic lane polarity reversal feature and an optional automatic lane order reversal feature. A user that desires to create a protocol-compliant integra... | 04/17/2012 |
| 8161267 | Methods and apparatus for scalable array processor interrupt detection and response Hardware and software techniques for interrupt detection and response in a scalable pipelined array processor environment are described. Utilizing these techniques, a sequential program execution model with interrupts can be maintained in a highly parallel scalable ... | 04/17/2012 |
| 8159277 | Techniques for providing multiple delay paths in a delay circuit A feedback loop circuit includes a phase detector and delay circuits. The phase detector generates an output signal based on a delayed periodic signal. The delay circuits are coupled in a delay chain that delays the delayed periodic signal. Each of the delay circuit... | 04/17/2012 |
| 8159044 | Density transition zones for integrated circuits An integrated circuit is provided with a spiral inductor and a transition zone surrounding the spiral inductor. The transition zone may have a geometry that is substantially eight-sided or octagonal. Metal layers in the transition zone may have metal fill that is su... | 04/17/2012 |
| 8158890 | Method and apparatus for low inductive design pattern Provided is an interleaved or wavy spatial arrangement of the micro-vias providing the electrical pathways for the power and ground leads are described. The spatial arrangement increases the coupling pairs between power and ground vias or leads. This spatial arrange... | 04/17/2012 |
| 8156463 | Method and apparatus for utilizing long-path and short-path timing constraints in an electronic-design-automation tool for routing A method for designing a system includes determining minimum and maximum delay budgets for connections. Routing resources are selected for connections in response to the minimum and maximum delay budgets. ... | 04/10/2012 |
| 8156452 | Method and apparatus for importing hardware description language into a system level design environment A method for importing a design in hardware description language (HDL) into a system level design tool includes setting a sampling time. The simulation model template is generated with the sampling time according to a selected simulation model type. ... | 04/10/2012 |
| 8156355 | Systems and methods for reducing static and total power consumption A method and system for reducing power consumption in a programmable logic device (PLD) is provided. The power consumption may be reduced by preferably continually considering power consumption as a factor in circuit design during the technology mapping, routing, an... | 04/10/2012 |
| 8156261 | Methods and apparatus for providing data transfer control A variety of advantageous mechanisms for improved data transfer control within a data processing system are described. A DMA controller is described which is implemented as a multiprocessing transfer engine supporting multiple transfer controllers which may work ind... | 04/10/2012 |
| 8156171 | Digital logic circuit In one aspect, there is provided a digital logic circuit that comprises circuitry for generating a new iteration xn+1 of the reciprocal square root of A from the previous iteration xn by (i) multiplying the previous iteration xn by t... | 04/10/2012 |
| 8155180 | Adaptive equalization methods and apparatus A system includes a programmable transmitter device (e.g., a PLD) connected to a programmable receiver device (e.g., another PLD) via a transmission medium for transmitting a high-speed data signal from the transmitter to the receiver. During a test mode of operatio... | 04/10/2012 |
| 8154942 | Integrated circuits with fuse programming and sensing circuitry Circuitry on an integrated circuit is provided that may be used to program fuses such as polysilicon fuses. Fuse programming may be performed using an elevated power supply voltage. Other circuitry on the integrated circuit may be powered using a standard power supp... | 04/10/2012 |
| 8154912 | Volatile memory elements with soft error upset immunity Memory elements are provided that exhibit immunity to soft error upset events when subjected to high-energy atomic particle strikes. The memory elements may each have ten transistors including two address transistors and four transistor pairs that are interconnected... | 04/10/2012 |
| 8154328 | Techniques for measuring phases of periodic signals A phase detector circuit generates a phase comparison signal based on a phase difference between first and second periodic signals during a test mode. Phases of the first and the second periodic signals do not change in response to variations in a signal generated b... | 04/10/2012 |
