Assignee: Advanced Semiconductor Engineering, Inc.

Location: Kaoshiung, TW
No. of patents: 35

Number	Title	Issue Date
7829977	Low temperature co-fired ceramics substrate and semiconductor package A low-temperature co-fired ceramics (LTCC) substrate includes a plurality of substrate units and at least one cutting pattern. The cutting pattern is disposed between neighboring two of the substrate units. A semiconductor package including the LTCC substrate is als...	11/09/2010
7514771	Leadless lead-frame A leadless lead-frame mainly includes a chip paddle and a plurality of leads. The chip paddle has chip disposal areas, and a grounding area surrounding the chip disposal area. The grounding area has a recession with a recession-bottom and a recession-wall connecting...	04/07/2009
7491568	Wafer level package and method for making the same The present invention relates to a wafer level package and method for making the same. The method of the invention comprises: (a) providing a metal layer, the metal layer having a first surface and a second surface; (b) forming a plurality of first caves and a plura...	02/17/2009
7446409	Cavity-down multiple-chip package A cavity-down multiple-chip package mainly includes a heat spreader, a circuit substrate with an opening, a chip, and at least one electronic element; wherein an upper surface of the circuit substrate defines at least one element mounting area; the heat spreader is ...	11/04/2008
7446404	Three-dimensional package and method of making the same A three-dimensional package including a first wafer having at least one first pad and a first protection layer exposing the first pad. A first hole penetrates the first wafer. A first isolation layer is disposed on the side wall of the first hole. The lower end of a...	11/04/2008
7446397	Leadless semiconductor package A leadless semiconductor package includes a lead frame, an adhesive, a chip, a plurality of first electrically conductive wires and a plurality of second electrically conductive wires. In this case, the lead frame has a chip paddle, a plurality of leads surrounding ...	11/04/2008
7429342	Method for cleaning and regenerating a mold A cleaning substrate for cleaning and regenerating a mold is disclosed. The mold is contaminated after repeatedly packaging the semiconductor device by making use of thermosetting resin. At least a protrusion of the substrate can substantially match with and be cont...	09/30/2008
7416919	Method for wafer level stack die placement A method for wafer level stack die placement is disclosed. At first, a wafer including a plurality of dice is provided. The wafer is adhered to a photosensitive adhesive tape. The wafer is attached on a die carrier to fix at least one die from the wafer on the die c...	08/26/2008
7368806	Flip chip package with anti-floating structure A flip chip package with an anti-floating structure includes a leadframe, a flip chip, and a plurality of solders. The leadframe includes a plurality of leads and a fastening part. At least one locking hole is formed on an upper surface of the fastening part. The fl...	05/06/2008
7365422	Package of leadframe with heatsinks A package of a leadframe with heatsinks, including a leadframe, a die, a first heatsink and a second heatsink. The leadframe has a die pad and a plurality of leads, and the leads are disposed around the die pad. The die is disposed on the die pad. The first heatsink...	04/29/2008
7352056	Semiconductor package structure with microstrip antennan A semiconductor package structure with a microstrip antenna comprises a packaging substrate, a chip and a microstrip radiation device. The packaging substrate has an upper surface having a packaging area on which the chip is disposed and a peripheral area on which t...	04/01/2008
7326590	Method for manufacturing ball grid array package A method for manufacturing a ball grid array package includes the steps of providing a substrate strip having a plurality of sub-substrate strips wherein each has an upper surface and a lower surface, disposing a plurality of chips on the upper surfaces of the sub-s...	02/05/2008
7291926	Multi-chip package structure The present invention relates to a multi-chip package structure, comprising a first substrate, a first chip, a sub-package and a first molding compound. The first chip is attached to the first substrate. The first molding compound encapsulates the first chip, the su...	11/06/2007
7291924	Flip chip stacked package A flip chip stacked package mainly comprises a carrier, a lower chip, an upper chip, a plurality of bumps, a plurality of bonding wires and a supporter. The supporter is attached to the lower surface of the carrier via an adhesive and covers the opening of the carri...	11/06/2007
7268418	Multi-chips stacked package A multi-chips stacked package at least comprises a substrate, a lower chip, an upper chip, an adhesive layer, a supporting body and an encapsulation. The lower chip is disposed on the substrate and the upper chip is attached to the lower chip via the adhesive layer....	09/11/2007
7262497	Bumpless assembly package A bumpless assembly package mainly comprises a substrate, and a chip. The substrate has an upper surface and an opposite lower surface, a plurality of first contacts and a plurality of second contacts formed on the upper surface of the substrate, wherein one of the ...	08/28/2007
7261828	Bumping process A method of forming a plurality of bumps over a wafer mainly comprises providing the wafer having a plurality of bonding pads formed thereon, forming an under bump metallurgy (UBM) layer over the bonding pads wherein the UBM layer includes an adhesive layer, for exa...	08/28/2007
7253529	Multi-chip package structure The present invention relates to a multi-chip package structure, comprising a first substrate, a first chip, a sub-package and a first molding compound. The first chip is attached to the first substrate. The first molding compound encapsulates the first chip, the su...	08/07/2007
7250677	Die package structure The present invention relates to a die package structure. The package structure comprises a first substrate, a first die, a sub-package and a first molding compound. The first die is disposed on the first substrate. The sub-package comprises a second substrate, a se...	07/31/2007
7251576	System and method for testing CMOS image sensor A system and method for testing CMOS image sensors includes a test supporter, a light source controller, an interface card and an image processor. The test supporter supports a CMOS image sensor under test. The light source controller provides a test light to the CM...	07/31/2007
7235989	Electrical test device having isolation slot An electrical test device including a substrate and a plurality of test pads. The test pads are disposed on a second surface of the substrate. Each test pad has a test hole, and first and second isolation slots. The first isolation slot is disposed on the periphery ...	06/26/2007
7235426	Method of backside grinding a bumped wafer A method for backside grinding a bumped wafer is disclosed. A wafer has a plurality of bumps formed on the active surface thereof. Prior to grinding the back surface of the wafer, a hot-melt adhesive layer is formed on the active surface of the wafer so as to be adh...	06/26/2007
7221041	Multi-chips module package and manufacturing method thereof A multi-chips module package comprises a lead frame, a first chip, a second chip, a plurality of electrically conductive wires and an encapsulation. The lead frame has a plurality of first leads, second leads and chip pads connecting to the first leads. The first ch...	05/22/2007
7218006	Multi-chip stack package A multi-chip stack package mainly includes a substrate, a first chip, a redistribution structure and at least one second chip. The first chip is disposed on the substrate with an active surface facing upwards. The redistribution structure includes a plurality of fir...	05/15/2007
7193282	Contact sensor package A contact sensor chip package includes a substrate, a contact sensor chip, a ground member and an encapsulation. The contact sensor chip is disposed on the substrate, and the contact sensor chip has a sensor area. The ground member is disposed on the ground pad of t...	03/20/2007
7193302	Leadless semiconductor package A leadless semiconductor package mainly comprises a leadless lead-frame, a chip, a silver paste and a plurality of electrically conductive wires. The lead frame includes a chip paddle and a plurality of leads surrounding the chip paddle wherein the chip paddle has a...	03/20/2007
7187070	Stacked package module A Stackable package module comprises a plurality of semiconductor devices in stack. One of the semiconductor devices includes a chip with an active surface and a corresponding back surface, a plurality of solder bumps and a plurality of stud bumps. The solder bumps ...	03/06/2007
7169651	Process and lead frame for making leadless semiconductor packages A process for making a plurality of leadless packages is disclosed. Firstly, chips are attached onto a lead frame with a first metal layer formed thereon. After a wire bonding step and an encapsulating step are conducted, a portion of each lead of the lead frame is ...	01/30/2007
7041534	Semiconductor chip package and method for making the same A semiconductor chip package mainly includes a semiconductor chip, a first dielectric layer disposed on the semiconductor chip, a plurality of conductive traces electrically connected to the semiconductor chip, a second dielectric layer disposed on the conductive tr...	05/09/2006
7037750	Method for manufacturing a package A method of manufacturing a package is disclosed. The manufacturing method includes the steps of providing a substrate having an opening, disposing a metal slice on a bottom surface of the substrate to cover the opening and bond pads on the bottom surface of the sub...	05/02/2006
6875683	Method of forming bump A method of forming a bump on an active surface of a wafer is disclosed. The method of the invention forms an under ball metallurgy (UBM) onto the active surface of the wafer. Then, the UBM is partially removed until a portion of the active surface of the wafer is e...	04/05/2005
6861761	Multi-chip stack flip-chip package A multi-chip stack flip-chip package comprises a substrate and a chip assembly on the substrate. The chip assembly includes a dummy chip and a flip chip. The dummy chip has a redistribution layer that has a plurality of bump pads for mounting the flip chip, a plural...	03/01/2005
6844617	Packaging mold with electrostatic discharge protection The present invention relates to a packaging mold with electrostatic discharge protection, comprising at least one recess for receiving at least one packaging substrate, the packaging substrate comprising an outer wall with a first height, the recess comprising an i...	01/18/2005
6627481	Method of manufacturing a semiconductor package with a lead frame having a support structure The present invention relates to a method of manufacturing semiconductor packages and products thereof. The method of manufacturing comprises steps of: (a) providing a lead frame which comprises a die pad, a plurality of connecting parts and a plurality o...	09/30/2003
6400004	Leadless semiconductor package A leadless semiconductor package mainly comprises a semiconductor chip disposed on a die pad and electrically connected to a plurality of leads arranged around the die pad. There are a plurality of tie bars connected to the die pad. The lower surface of e...	06/04/2002

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Assignee: Advanced Semiconductor Engineering, Inc.