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| Number | Title | Issue Date |
| 8185695 | Snoop filtering mechanism A system and method for selectively transmitting probe commands and reducing network traffic. Directory entries are maintained to filter probe command and response traffic for certain coherent transactions. Rather than storing directory entries in a dedicated direct... | 05/22/2012 |
| 8184704 | Spatial filtering of differential motion vectors Embodiments include a video data encoding method comprising receiving video input frames, and performing motion estimation on the video received frames. The motion estimation comprises performing a hierarchical motion search to find motion vectors with optimum sum o... | 05/22/2012 |
| 8184477 | Semiconductor switching device A switching device and methods of making and operating the same are provided. In one aspect, a method of operating a switching device is provided that includes providing a MOS transistor that has a gate, a source region, a drain region and a body region. A bipolar t... | 05/22/2012 |
| 8184118 | Depth operations Described are a video graphics system, graphics processor, and methods for rendering three-dimensional objects. A buffer is partitioned into tiles of pixels. Each pixel of each tile includes at least one sample. A primitive is received and determined to fully cover ... | 05/22/2012 |
| 8184117 | Stencil operations Described are a video graphics system, graphics processor, and methods for rendering three-dimensional objects. A buffer is partitioned into tiles of pixels. Each pixel of each tile includes at least one sample. A primitive is received and determined to cover fully ... | 05/22/2012 |
| 8181005 | Hybrid branch prediction device with sparse and dense prediction caches A system and method for branch prediction in a microprocessor. A hybrid device stores branch prediction information in a sparse cache for no more than a common smaller number of branches within each entry of the instruction cache. For the less common case wherein an... | 05/15/2012 |
| 8180947 | USB on-the-go controller A USB (Universal Serial Bus) controller technique for implementing OTG (On-The-Go) functionality is provided. The device may have an EHCI (Enhanced Host Controller Interface) compliant host control unit, and an OTG control unit to implement an OTG state machine part... | 05/15/2012 |
| 8180944 | Guest interrupt manager that records interrupts for guests and delivers interrupts to executing guests In an embodiment, a system comprises a memory system and a guest interrupt manager. The guest interrupt manager is configured to receive an interrupt message corresponding to an interrupt that is targeted at a guest executable on the system. The guest interrupt mana... | 05/15/2012 |
| 8169242 | Programmable fine lock/unlock detection circuit An integrated circuit includes a feedback controlled clock generating circuit, such as a DLL, PLL or other suitable circuit, that is operative to provide a feedback reference frequency signal based on a generated output clock signal. The integrated circuit also incl... | 05/01/2012 |
| D658607 | Circuit package lid | 05/01/2012 |
| 8166276 | Translate and verify instruction for a processor In an embodiment, a first instruction is defined that comprises at least a first operand from which the execution core is configured to determine a virtual address and a second operand that specifies one or more translation attributes that exist in a page table entr... | 04/24/2012 |
| 8161209 | Peer-to-peer special purpose processor architecture and method A peer-to-peer special purpose processor architecture and method is described. Embodiments include a plurality of special purpose processors coupled to a central processing unit via a host bridge bus, a direct bus directly coupling each of the plurality of special p... | 04/17/2012 |
| 8160089 | Dynamic inter packet gap generation system and method The present invention facilitates network throughput by dynamically generating IPG values, which are employed when recovering from network collisions. Testing a number of IPG values and tracking collisions that occur as a result for each value generate the IPG value... | 04/17/2012 |
| 8159440 | Controller driver and display apparatus using the same A controller/driver is composed of a work memory, a graphic engine, a display memory, and a driver circuit. The graphic engine converts externally received image data into first bitmap data, and stores the first bitmap data in the work memory. The display memory rec... | 04/17/2012 |
| 8156314 | Incremental state updates A system and method are described that manage incremental state updates in such a way that multiple threads within a processor can each operate, in effect, on their own set of state data. The system and method are applicable to any processor in which multiple thread... | 04/10/2012 |
| 8156286 | Processor and method for using an instruction hint to prevent hardware prefetch from using certain memory accesses in prefetch calculations A microprocessor includes a cache memory, a prefetch unit, and detection logic. The prefetch unit may be configured to monitor memory accesses that miss in the cache and to determine whether to prefetch one or more blocks of memory from a system memory based upon pr... | 04/10/2012 |
| 8154564 | Dynamically configurable bilinear filtering system Apparatus and methods for a bilinear filter system comprising a pre-formatter module, a bilinear module, an accumulator module, and a format module. The pre-formatter module is configured to receive texel data and convert it to a normalized fixed point format. The b... | 04/10/2012 |
| 8149024 | Dual function voltage and current mode differential driver A dual function differential driver includes a voltage mode differential driver portion and a current mode differential driver portion. Control circuitry is connected to the voltage mode differential driver portion and the current mode differential driver portion. T... | 04/03/2012 |
| 8145876 | Address translation with multiple translation look aside buffers A data processing device employs a first translation look-aside buffer (TLB) to translate virtual addresses to physical addresses. If a virtual address to be translated is not located in the first TLB, the physical address is requested from a set of page tables. Whe... | 03/27/2012 |
| 8144585 | Data processing device interface and methods thereof A method of receiving communications at a data processing device includes receiving a packet from a virtual channel associated with a physical communication link. The packet is associated with a link virtual channel, and is stored in a storage location with the link... | 03/27/2012 |
| 8143661 | Memory cell system with charge trap A memory cell system is provided including a first insulator layer over a semiconductor substrate, a charge trap layer over the first insulator layer, and slot where the charge trap layer includes a second insulator layer having the characteristic of being grown. | 03/27/2012 |
| 8139632 | Video decoder with adaptive outputs In one aspect, there is provided a video decoder including a first write port to write uncompressed video data to a first buffer in a first format adapted based on an input required by the video decoder and to suppress writing to the first buffer. The video decoder ... | 03/20/2012 |
| 8135935 | ECC implementation in non-ECC components A method and apparatus for implementation of error correction code (ECC) checking in non-ECC-compliant components. The method includes receiving a logical address, wherein the logical address maps to first and second physical addresses of a memory. The first and sec... | 03/13/2012 |
| 8134569 | Aperture compression for multiple data streams A hardware-based aperture compression system permits addressing large memory spaces via a limited bus aperture. Streams are assigned dynamic base addresses (BAR) that are maintained in registers on sources and destinations. Requests for addresses lying between BAR a... | 03/13/2012 |
| 8134417 | Automatic amplitude control for voltage controlled oscillator A circuit and method for calibrating a VCO (voltage controlled oscillator) is disclosed. In one embodiment, a circuit includes a VCO and a bias control circuit coupled to a tail node of the VCO. An amplitude control unit may also be coupled to the tail node, wherein... | 03/13/2012 |
| 8124448 | Semiconductor chip with crack deflection structure Various die crack deflection structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes fabricating a semiconductor chip including an outer edge, a first side and a second side opposite to the first si... | 02/28/2012 |
| 8117498 | Mechanism for maintaining cache soft repairs across power state transitions A processor core includes one or more cache memories and a repair unit. The repair unit may repair locations in the cache memories identified as having errors during an initialization sequence. The repair unit may further cause information corresponding to the repai... | 02/14/2012 |
| 8108175 | Method for determining self-heating free I-V characterstics of a transistor According to one exemplary embodiment, a method for determining a self-heating free drain current in a transistor corresponding to a channel temperature not affected by a drain DC current includes measuring at least three unique drain currents of a transistor corres... | 01/31/2012 |
| 8103979 | System for generating and optimizing mask assist features based on hybrid (model and rules) methodology An optimal assist feature rules set for an integrated circuit design layout is created using inverse lithography. The full chip layout is lithographically simulated, and printability failure areas are determined. The features are analyzed for feature layout patterns... | 01/24/2012 |
| 8103788 | Method and apparatus for dynamically reallocating buffers for use in a packet transmission Various embodiments of systems and methods for dynamically reallocating buffers used in communicating packets in various communication channels are disclosed. In some embodiments, a method may involve transmitting packets in several communication channels dependent ... | 01/24/2012 |
| 8102633 | Power supply equalization circuit using distributed high-voltage and low-voltage shunt circuits Embodiments of an IC protection circuit that protects low voltage supply transistors and circuits within the IC from excessive power supply levels and ESD events are described. A protection circuit situated between the IO pins of the IC and the internal circuitry of... | 01/24/2012 |
| 8102632 | Electrostatic discharge power clamp trigger circuit using low stress voltage devices Embodiments of an IC protection circuit that protects low voltage supply transistors and circuits within the IC from excessive power supply levels and ESD events are described. A protection circuit situated between the IO pins of the IC and the internal circuitry of... | 01/24/2012 |
| 8102009 | Integrated circuit eliminating source/drain junction spiking An integrated circuit with a semiconductor substrate is provided. A gate dielectric is on the semiconductor substrate, and a gate is on the gate dielectric. A metallic layer is on the semiconductor substrate, and the metallic layer is reacted with the semiconductor ... | 01/24/2012 |
| 8094476 | Content addressable memory match signal test device and methods thereof A content addressable memory (CAM) of a data processing device can operate in a normal mode or a test mode. In the normal mode, the CAM provides a match value in response to determining that a received data value matches one of a plurality of values stored at memory... | 01/10/2012 |
| 8089125 | Integrated circuit system with triode An integrated circuit system includes an integrated circuit, forming a triode near the integrated circuit, and attaching a connector to the triode and the integrated circuit. ... | 01/03/2012 |
| 8086825 | Processing pipeline having stage-specific thread selection and method thereof One or more processor cores of a multiple-core processing device each can utilize a processing pipeline having a plurality of execution units (e.g., integer execution units or floating point units) that together share a pre-execution front-end having instruction fet... | 12/27/2011 |
| 8082425 | Reliable execution using compare and transfer instruction on an SMT machine A system and method for efficient reliable execution on a simultaneous multithreading machine. A processor is placed in a reliable execution mode (REM) to detect possible errors during execution of a software application. Only two threads may be configured to operat... | 12/20/2011 |
| 8078792 | Separate page table base address for minivisor In one embodiment, a processor supports an alternate address space during execution of non-guest code (such as a minivisor or a virtual machine monitor (VMM)). The alternate address space may be the guest address space. An instruction in the minivisor/VMM may specif... | 12/13/2011 |
| 8072252 | Compound logic flip-flop having a plurality of input stages A compound logic flip-flop. The flip-flop includes a plurality of input stages, wherein each of the input stages is coupled to receive at least one input signal and a clock signal. Each of the plurality of input (i.e. ‘master’) stages is configured to perform a ... | 12/06/2011 |
| 8068114 | Mechanism for granting controlled access to a shared resource Disclosed are methods and systems for granting an application-specific integrated circuit (ASIC) in a multi-ASIC environment controlled access to a shared resource. A system includes a first ASIC, a second ASIC, and a shared memory that stores a shared resource and ... | 11/29/2011 |
