Assignee: Advanced Micro Devices, Inc.

Location: Not specified.
No. of patents: 153

Number	Title	Issue Date
7157131	Prevention of counterfeit markings on semiconductor devices A lidded semiconductor device has a first layer applied to the lid, which first layer is chosen of a material which fluoresces upon application of non-visible electromagnetic waves thereto, for example, ultraviolet light. A second layer is provided over the first la...	01/02/2007
7069103	Controlling cumulative wafer effects A method and apparatus provided for controlling cumulative wafer effects. The method comprises processing a workpiece, determining a cumulative effect of the processing on the workpiece and comparing the determined cumulative effect to a reference target value. The ...	06/27/2006
6978189	Matching data related to multiple metrology tools A method and an apparatus for matching data related to an integrated metrology tool and a standalone metrology tool. At least one semiconductor wafer is processed. An integrated metrology tool and/or a standalone metrology tool is matched based upon a difference bet...	12/20/2005
6664154	Method of using amorphous carbon film as a sacrificial layer in replacement gate integration processes An exemplary embodiment relates to a method of using amorphous carbon in replacement gate integration processes. The method can include depositing an amorphous carbon layer above a substrate, patterning the amorphous carbon layer, depositing a dielectric ...	12/16/2003
6271112	Interlayer between titanium nitride and high density plasma oxide A method for reducing die loss in a semiconductor fabrication process which employs titanium nitride and HDP oxide is provided. In the fabrication of multilevel interconnect structures, there is a propensity for defect formation in a process in which tita...	08/07/2001
6246774	Wavetable audio synthesizer with multiple volume components and two modes of stereo positioning A digital wavetable audio synthesizer including a synthesizer volume generator. The volume generator causing a data sample to be multiplied by volume components that add right offset, left offset, and effects volume to the data. The left and right offsets...	06/12/2001
6242776	Device improvement by lowering LDD resistance with new silicide process A method is provided for fabricating a semiconductor device on a structure, the method including forming a dielectric layer adjacent a gate conductor of the semiconductor device and above an LDD region of the structure and removing a first portion of the ...	06/05/2001
6230069	System and method for controlling the manufacture of discrete parts in semiconductor fabrication using model predictive control A system and method for controlling the manufacture of semiconductor wafers using model predictive control is provided. In accordance with one embodiment, a tool output of the manufacturing tool is determined based on a first wafer run. Using the tool out...	05/08/2001
6125055	Sector write protect CAMS for a simultaneous operation flash memory A simultaneous operation flash memory capable of write protecting predetermined sectors in the simultaneous operation flash memory. The preferred simultaneous operation flash memory includes a plurality of sectors divided into an upper bank and a sliding ...	09/26/2000
6093331	Backside silicon removal for face down chip analysis A method for the precise removal of the backside silicon on face down semiconductor devices to obtain a planar surface to allow electron beam microprobe analysis of the semiconductor device. The backside silicon is removed by plasma etching in a fluorocar...	07/25/2000
6030752	Method of stitching segments defined by adjacent image patterns during the manufacture of a semiconductor device A method of stitching segments defined by adjacent image patterns of a photolithographic system during the manufacture of a semiconductor device is disclosed. The method includes forming a material over a semiconductor substrate, projecting a first image ...	02/29/2000
6021314	Free channel selector for selecting an optimal channel A free channel selector for selecting from a plurality of channels an optimal channel for establishing radio communication. The channels may be selected by a radio frequency (RF) module for outputting sampled signals carried on that channel. The selected ...	02/01/2000
5998293	Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect An improved multilevel interconnect structure is provided. The interconnect structure includes pillars spaced from each other across a wafer. The pillars are placed between levels of interconnect or between an interconnect level and a semiconductor substr...	12/07/1999
5996051	Communication system which in a first mode supports concurrent memory acceses of a partitioned memory array and in a second mode supports non-concurrent memory accesses to the entire memory array A communication system is provided that includes a mechanism for selectively addressing memory banks depending upon the configuration of that system. The communication system can therefore operate in accordance with two possible modes of operation. Accord...	11/30/1999
5981357	Semiconductor trench isolation with improved planarization methodology An isolation technique is provided for improving the overall planarity of filled isolation regions relative to adjacent silicon mesas. The isolation process results in a silicon mesa having enhanced mechanical and electrical properties. Planarity is perfo...	11/09/1999
5978865	System for performing DMA transfers where an interrupt request signal is generated based on the value of the last of a plurality of data bits transmitted A microcontroller is presented which is configurable to transfer data to and from one or more asynchronous serial ports (ASPs) using direct memory access (DMA), and having hardware features which cause each ASP to notify the microprocessor core (i.e., exe...	11/02/1999
5976952	Implanted isolation structure formation for high density CMOS integrated circuits A semiconductor process in which oxygen is selectively implanted into isolation regions of a semiconductor substrate and subsequently annealed to form isolation structures within the isolation regions. Preferably, a semiconductor substrate is provided and...	11/02/1999
5972124	Method for cleaning a surface of a dielectric material The present invention provides a method for cleaning particles from a semiconductor topography that has been polished using a fixed-abrasive polishing process by applying a cleaning solution including either (a) an acid and a peroxide or (b) an acid oxida...	10/26/1999
5970375	Semiconductor fabrication employing a local interconnect An integrated circuit fabrication process is provided in which a sub-level local interconnect is formed between a gate conductor of one transistor and a junction of another transistor. The formation of a sub-level local interconnect allows for higher pack...	10/19/1999
5963783	In-line detection and assessment of net charge in PECVD silicon dioxide (oxide) layers The present method provides for the detection and assessment of the net charge in a PECVD oxide layer deposited on a surface of a semiconductor substrate. Electrical potential differences across PECVD oxide layers on as-produced semiconductor substrates a...	10/05/1999
5961581	Method and circuit for detecting address limit violations in a microprocessor-based computer An address limit violation detection circuit in a microprocessor-based computer system for eliminating delay between the generation of a definite limit violation (DLV) signal and the generation of a potential limit violation signal. The detection circuit ...	10/05/1999
5959337	Air gap spacer formation for high performance MOSFETs A method is provided for forming a transistor in which capacitive coupling between the gate conductors and adjacent structures employed by the integrated circuit is reduced. According to an embodiment, a gate conductor is dielectrically spaced above a sem...	09/28/1999
5959333	Reduction of dopant diffusion by the co-implantation of impurities into the transistor gate conductor Diffusion of dopants within the gate of the transistor and/or the source/drain regions can be inhibited by the ion co-implantation of impurities in addition to the ion implantation of the n-type or p-type dopants. Implanting a combination of nitrogen and ...	09/28/1999
5955785	Copper-containing plug for connection of semiconductor surface with overlying conductor An integrated circuit fabrication process is provided in which copper is used as the contact plug material for a via. The via is a hole etched through an interlevel dielectric which is disposed upon a semiconductor topography, e.g., a silicon-based substr...	09/21/1999
5953626	Dissolvable dielectric method A fabrication process that produces an air gap dielectric in which a multi-level interconnect structure is formed upon a temporary supporting material. The temporary material is subsequently dissolved away leaving behind an intralevel and an interlevel di...	09/14/1999
5950091	Method of making a polysilicon gate conductor of an integrated circuit formed as a sidewall spacer on a sacrificial material A gate conductor structure and method for forming the structure are provided whereby the overall gate length can be made with less susceptibility to lithography variations. The gate conductor is produced by defining a sidewall surface region and then form...	09/07/1999
5950082	Transistor formation for multilevel transistors A dual level transistor and a fabrication technique for making the transistor. The dual level transistor is an integrated circuit in which a first transistor is formed on an upper surface of a global dielectric and a second transistor is formed on an uppe...	09/07/1999
5949126	Trench isolation structure employing protective sidewall spacers upon exposed surfaces of the isolation trench A shallow trench isolation structure and method for making the same are presented. In an embodiment, a trench dielectric is formed within a shallow trench that is disposed in a semiconductor substrate comprising single-crystalline silicon. Dielectric spac...	09/07/1999
5948219	Apparatus for selectively exposing a semiconductor topography to an electric field A lithographic apparatus and method are presented which use an electric field to form features from a desired material upon an upper topography of a semiconductor substrate. A layer of an electric field resist material is formed over a layer of the desire...	09/07/1999
5946579	Stacked mask integration technique for advanced CMOS transistor formation A method for forming a gate conductor by using a masking layer above a polysilicon layer to define the length of a gate is presented. The length of the gate may be adjusted by the use of spacers. The method includes forming a plurality of layers including...	08/31/1999
5943585	Trench isolation structure having low K dielectric spacers arranged upon an oxide liner incorporated with nitrogen A process is provided for forming a trench isolation structure which includes dielectric spacers composed of a dielectric material having a relatively low dielectric constant, K, that is approximately less than 3.8. The capacitance between active areas se...	08/24/1999
5943562	Semiconductor fabrication employing a transistor gate coupled to a localized substrate A method is provided for forming a transistor in which the gate is coupled to a second substrate dielectrically spaced above a first substrate. According to an embodiment, a polysilicon layer is formed across an interposing dielectric layer which is dispo...	08/24/1999
5943481	Computer communication network having a packet processor with subsystems that are variably configured for flexible protocol handling A communication system is provided that includes a mechanism for recognizing various communication protocols. That is, the communication system employs a packet processor which can adapt to sent and receive numerous protocols. The packet processor forms a...	08/24/1999
5940707	Vertically integrated advanced transistor formation A field-effect transistor and method for making same in which a first source/drain impurity distribution is located at a first depth below an upper surface of the semiconductor substrate and a second source/drain impurity distribution is located at a seco...	08/17/1999
5937308	Semiconductor trench isolation structure formed substantially within a single chamber A substantially in situ trench isolation process is provided. The process includes forming a trench regions between active regions in a semiconductor substrate. The semiconductor substrate may be covered with a protective oxide pad and/or nitride layer. I...	08/10/1999
5936287	Nitrogenated gate structure for improved transistor performance and method for making same An integrated circuit fabrication method incorporating nitrogen into the polysilicon-dielectric interface in an MOS transistor. A semiconductor substrate having a P-well region and an N-well region is provided. Each well region includes channel regions an...	08/10/1999
5932013	Apparatus for cleaning a semiconductor processing tool A method and apparatus for cleaning apertures within an input manifold of a semiconductor fabrication deposition tool is presented. Vapor phase chemicals that contain the required constituents are introduced into the tool through the input manifold. The a...	08/03/1999
5930620	Resistance to gate dielectric breakdown at the edges of shallow trench isolation structures A semiconductor process in which at least one isolation structure is formed in a semiconductor substrate. An oxygen bearing species is introduced into portions of the semiconductor substrate proximal to the isolation structure. A gate dielectric layer is ...	07/27/1999
5926713	Method for achieving global planarization by forming minimum mesas in large field areas An isolation technique is provided for improving the overall planarity of trench isolation regions relative to adjacent silicon mesas. The isolation process results in a spaced plurality of silicon risers formed in wide isolation regions. The space betwee...	07/20/1999
5924833	Automated wafer transfer system An automated system is presented for containerless transfer of semiconductor wafers through a wall separating a first fabrication area and a second fabrication area. The system includes multiple containers for transporting the wafers, one or more air lock...	07/20/1999

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Assignee: Advanced Micro Devices, Inc.