Quotables
"The idea that cavalry will be replaced by these iron coaches is absurd. It is little short of treasonous."
Aide-de-camp to Field Marshal Haig ; At a tank demonstration, 1916
PatentStorm News
Make the Most of Our Site
See this month's Top Inventors and Most Cited Patents.
Stay on top of the latest innovations by subscribing to an RSS feed.
Registered users: Manage your profile.
| Number | Title | Issue Date |
| 8185230 | Method and apparatus for predicting device electrical parameters during fabrication A method includes providing a set of initial characteristic values associated with the semiconductor device. A first fabrication process is performed on the semiconductor device. Fabrication data associated with the first fabrication process is collected. At least o... | 05/22/2012 |
| 8183605 | Reducing transistor junction capacitance by recessing drain and source regions By recessing portions of the drain and source areas on the basis of a spacer structure, the subsequent implantation process for forming the deep drain and source regions may result in a moderately high dopant concentration extending down to the buried insulating lay... | 05/22/2012 |
| 8183101 | Multiple gate transistor having fins with a length defined by the gate electrode The drain and source regions of a multiple gate transistor may be formed without an epitaxial growth process by using a placeholder structure for forming the drain and source dopant profiles and subsequently masking the drain and source areas and removing the placeh... | 05/22/2012 |
| 8183100 | Transistor with embedded SI/GE material having enhanced across-substrate uniformity In sophisticated semiconductor devices, a strain-inducing semiconductor alloy may be positioned close to the channel region by forming cavities on the basis of a wet chemical etch process, which may have an anisotropic etch behavior with respect to different crystal... | 05/22/2012 |
| 8183096 | Static RAM cell design and multi-contact regime for connecting double channel transistors A static RAM cell may be formed on the basis of two double channel transistors and a select transistor, wherein a body contact may be positioned laterally between the two double channel transistors in the form of a dummy gate electrode structure, while a further rec... | 05/22/2012 |
| 8182709 | CMP system and method using individually controlled temperature zones By creating a temperature profile across a polishing pad, a respective temperature profile may be obtained in a substrate to be polished, which may result in a respective varying removal rate across the substrate for a chemically reactive slurry material or for an e... | 05/22/2012 |
| 8173538 | Method of selectively forming a conductive barrier layer by ALD By providing a surface modification process prior to or during a self-limiting deposition process, the per se highly conformal deposition behavior may be selectively changed so as to obtain reliable coverage at specific surface areas, while significantly reducing or... | 05/08/2012 |
| 8163594 | Semiconductor device comprising a carbon-based material for through hole vias In a semiconductor device, a through hole via extending through the substrate of the device may be formed on the basis of a carbon-containing material, thereby providing excellent compatibility with high temperature processes, while also providing superior electrica... | 04/24/2012 |
| 8163571 | Multi-step deposition control For providing control of two-step or a multi-step deposition process, a method and a corresponding deposition system is provided comprising providing a deposition process having at least two sub-processes employing different sets of process parameters, wherein each ... | 04/24/2012 |
| 8158486 | Trench isolation structure having different stress By locally heating isolation trenches with different annealing conditions, a different magnitude of intrinsic stress may be obtained in different isolation trenches. In some illustrative embodiments, the different anneal temperature may be achieved on the basis of a... | 04/17/2012 |
| 8158065 | In situ monitoring of metal contamination during microstructure processing By providing a tool internal sensor device in a process tool in a semiconductor facility, metal contamination may be monitored in situ, thereby avoiding or at least significantly reducing the requirement for sophisticated sample preparation techniques, such as vapor... | 04/17/2012 |
| 8153524 | Providing superior electromigration performance and reducing deterioration of sensitive low-k dielectrics in metallization systems of semiconductor devices During the formation of complex metallization systems, a conductive cap layer may be formed on a copper-containing metal region in order to enhance the electromigration behavior without negatively affecting the overall conductivity. At the same time, a thermo chemic... | 04/10/2012 |
| 8153351 | Methods for performing photolithography using BARCs having graded optical properties Photolithography methods using BARCs having graded optical properties are provided. In an exemplary embodiment, a photolithography method comprises the steps of depositing a BARC overlying a material to be patterned, the BARC having a refractive index and an absorba... | 04/10/2012 |
| 8149384 | Method and apparatus for extracting dose and focus from critical dimension data A method for monitoring a photolithography system includes defining a model of the photolithography system for modeling top and bottom critical dimension data associated with features formed by the photolithography system as a function of dose and focus. A library o... | 04/03/2012 |
| 8147670 | Profile control on ring anode plating chambers for multi-step recipes The present disclosure generally addresses the problem of controlling a plating profile in multi-step recipes and addresses, in particular, the problem of compensating for variations of the plating tool state to stabilize the plating results. The compensation is don... | 04/03/2012 |
| 8143133 | Technique for enhancing dopant profile and channel conductivity by millisecond anneal processes During the fabrication of advanced transistors, significant dopant diffusion may be suppressed by performing a millisecond anneal process after completing the basic transistor configuration, wherein a stress memorization technique may also be obtained by forming a s... | 03/27/2012 |
| 8127057 | Multi-level buffering of transactional data An apparatus, method, and system for implementing a hardware transactional memory (HTM) system with multiple levels of transactional buffers. The apparatus comprises a data cache configured to buffer data in a shared (by a plurality of processing cores) memory acces... | 02/28/2012 |
| 8126588 | Method and system for controlling transport sequencing in a process tool by a look-ahead mode By providing a look-ahead functionality for a tool internal substrate handling system of process tools on the basis of a process history, the tool internal substrate sequencing may be significantly enhanced. The look-ahead functionality enables a prediction of proce... | 02/28/2012 |
| 8124532 | Semiconductor device comprising a copper alloy as a barrier layer in a copper metallization layer By forming a tin and nickel-containing copper alloy on an exposed copper surface, which is treated to have a copper oxide thereon, a reliable and highly efficient capping layer may be provided. The tin and nickel-containing copper alloy may be formed in a gaseous am... | 02/28/2012 |
| 8124473 | Strain enhanced semiconductor devices and methods for their fabrication A strain enhanced semiconductor device and methods for its fabrication are provided. One method comprises embedding a strain inducing semiconductor material in the source and drain regions of the device to induce a strain in the device channel. Thin metal silicide c... | 02/28/2012 |
| 8118932 | Technique for monitoring dynamic processes in metal lines of microstructures By locally heating specific scan positions within a region of interest and automatically obtaining respective measurement data in a time-resolved and spatially-resolved fashion, dynamic processes within a metallization layer of semiconductor devices may be efficient... | 02/21/2012 |
| 8114746 | Method for forming double gate and tri-gate transistors on a bulk substrate Three-dimensional transistor structures such as FinFETS and tri-gate transistors may be formed on the basis of an enhanced masking regime, thereby enabling the formation of drain and source areas, the fins and isolation structures in a self-aligned manner within a b... | 02/14/2012 |
| 8114688 | Method and semiconductor structure for monitoring etch characteristics during fabrication of vias of interconnect structures By forming a trench-like test opening above a respective test metal region during the etch process for forming via openings in a dielectric layer stack of sophisticated metallization structures of semiconductor devices, the difference in etch rate in the respective ... | 02/14/2012 |
| 8110498 | Method for passivating exposed copper surfaces in a metallization layer of a semiconductor device When forming sophisticated metallization systems, surface integrity of an exposed metal surface, such as a copper-containing surface, may be enhanced by exposing the surface to a vapor of a passivation agent. Due to the corresponding interaction with the metal surfa... | 02/07/2012 |
| 8110487 | Method of creating a strained channel region in a transistor by deep implantation of strain-inducing species below the channel region By incorporating a carbon species below the channel region of a P-channel transistor prior to the formation of the gate electrode structure, an efficient strain-inducing mechanism may provided, thereby enhancing performance of P-channel transistors. The position and... | 02/07/2012 |
| 8101524 | Technique for enhancing the fill capabilities in an electrochemical deposition process by edge rounding of trenches During the formation of a metal line in a low-k dielectric material, an upper portion of a trench formed in a capping layer and the low-k dielectric material is treated to provide enlarged tapering or corner rounding, thereby significantly improving the fill capabil... | 01/24/2012 |
| 8097536 | Reducing metal voids in a metallization layer stack of a semiconductor device by providing a dielectric barrier layer Metallization systems on the basis of copper and low-k dielectric materials may be efficiently formed by providing an additional dielectric material of enhanced surface conditions after the patterning of the low-k dielectric material. Consequently, defects such as i... | 01/17/2012 |
| 8097519 | SOI device having a substrate diode formed by reduced implantation energy By removing material during the formation of trench openings of isolation structures in an SOI device, the subsequent implantation process for defining the well region for a substrate diode may be performed on the basis of moderately low implantation energies, there... | 01/17/2012 |
| 8076209 | Methods for fabricating MOS devices having highly stressed channels Methods for forming a semiconductor device comprising a silicon-comprising substrate are provided. One exemplary method comprises depositing a polysilicon layer overlying the silicon-comprising substrate, amorphizing the polysilicon layer, etching the amorphized pol... | 12/13/2011 |
| 8071442 | Transistor with embedded Si/Ge material having reduced offset to the channel region A strain-inducing semiconductor alloy may be formed on the basis of cavities which may have a non-rectangular shape, which may be maintained even during corresponding high temperature treatments by providing an appropriate protection layer, such as a silicon dioxide... | 12/06/2011 |
| 8067315 | Microstructure device including a compressively stressed low-k material layer A nitrogen-containing silicon carbide material may be deposited on the basis of a single frequency or mixed frequency deposition recipe with a high internal compressive stress level up to 1.6 GPa or higher. Thus, this dielectric material may be advantageously used i... | 11/29/2011 |
| 8058081 | Method of testing an integrity of a material layer in a semiconductor structure A method comprises providing a semiconductor structure. The semiconductor structure comprises a feature comprising a first material and a layer of a second material formed over the feature. The semiconductor structure is exposed to an etchant. The etchant is adapted... | 11/15/2011 |
| 8056402 | Nanoprobe tip for advanced scanning probe microscopy comprising a layered probe material patterned by lithography and/or FIB techniques By forming an appropriate material layer, such as a metal-containing material, on a appropriate substrate and patterning the material layer to obtain a cantilever portion and a tip portion, a specifically designed nano-probe may be provided. In some illustrative asp... | 11/15/2011 |
| 8055533 | Method and apparatus for assigning material transport vehicle idle locations A method for determining parking assignments for material handling vehicles in a manufacturing system is provided. The manufacturing system is operable to perform fabrication processes on a plurality of loads. The method includes identifying at least one idle materi... | 11/08/2011 |
| 8051301 | Memory management system and method providing linear address based memory access security A memory management unit (MMU) is disclosed for managing a memory storing data arranged within a plurality of memory pages. The MMU includes a security check unit (SCU) receiving a linear address generated during execution of a current instruction. The linear addres... | 11/01/2011 |
| 8051093 | Method and apparatus for extracting data from a data store A method includes defining a general query for extracting data from at least one data store operable to store workpiece data associated with the processing of workpieces in a manufacturing system. The general query specifies at least one ambiguous parameter having a... | 11/01/2011 |
| 8050793 | Method and apparatus for linking reticle manufacturing data A method includes providing a design data file specifying at least one target feature on a first reticle. A reticle qualification data file specifying a plurality of feature measurements associated with features formed using the first reticle is provided. At least o... | 11/01/2011 |
| 8050077 | Semiconductor device with transistor-based fuses and related programming method A transistor-based fuse structure is realized in a semiconductor device having a semiconductor substrate, transistor devices formed on the semiconductor substrate, and the transistor-based fuse structure formed on the semiconductor substrate. The transistor-based fu... | 11/01/2011 |
| 8048811 | Method for patterning a metallization layer by reducing resist strip induced damage of the dielectric material By forming a hardmask layer in combination with one or more cap layers, undue exposure of a sensitive dielectric material to resist stripping etch ambients may be reduced and integrity of the hardmask may also be maintained so that the trench etch process may be per... | 11/01/2011 |
| 8048736 | Semiconductor device comprising a capacitor in the metallization system and a method of forming the capacitor By forming metal capacitors in the metallization structures of semiconductor devices, complex manufacturing sequences in the device level may be avoided. The process of manufacturing the metal capacitors may be performed on the basis of well-established patterning r... | 11/01/2011 |
