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| Number | Title | Issue Date |
| 6700404 | Tileable field-programmable gate array architecture An apparatus includes a field-programmable gate array (FPGA). The FPGA includes a first FPGA tile, and the first FPGA tile includes a plurality of functional groups (FGs), a third set of routing conductors, in addition to a first set of routing conductors... | 03/02/2004 |
| 6680624 | Block symmetrization in a field programmable gate array An FPGA architecture has top, middle and low levels. The top level of the architecture is an array of the B16×16 tiles arranged in a rectangular array and enclosed by I/O blocks on the periphery. On each of the four sides of a B16×16 tile, and also asso... | 01/20/2004 |
| 6678848 | Programming circuitry for configurable FPGA I/O In a one-time programmable FPGA, new circuitry interfaces between boundary scan registers and configurable I/O cells is disclosed incorporating the use of boundary scan registers for both addressing, and establishing the value of, individual programmable ... | 01/13/2004 |
| 6636930 | Turn architecture for routing resources in a field programmable gate array An FPGA architecture has top, middle and low levels. The top level of the architecture is an array of the B16×16 tiles arranged in a rectangular array and enclosed by I/O blocks on the periphery. A B16×16 tile in the middle level of hierarchy is a sixte... | 10/21/2003 |
| 6624657 | Block connector splitting in logic block of a field programmable gate array A logic block in a field programmable gate array comprises a plurality of clusters of logic devices. At least one of the logic devices in each of the clusters has an input or an output. A first set of interconnect conductors enters the logic block from a ... | 09/23/2003 |
| 6617875 | Programmable multi-standard I/O architecture for FPGAs The invention discloses an architecture for the input/output buffer section of an FPGA. It provides a convenient and efficient addressing scheme for addressing fuse matrices that are used to configure programmable input/output buffers in the FPGA. The pro... | 09/09/2003 |
| 6611153 | Tileable field-programmable gate array architecture An apparatus includes a field-programmable gate array (FPGA). The FPGA includes a first FPGA tile, and the first FPGA tile includes a plurality of functional groups (FGs), a regular routing structure, and a plurality of interface groups (IGs). The plurali... | 08/26/2003 |
| 6603187 | Antifuse structure suitable for VLSI application The present invention relates to a high performance, high reliability antifuse using conductive electrodes. According to first and second embodiments, the problem of switch-off in conductor-to-conductor antifuses is solved by utilizing conductive electrod... | 08/05/2003 |
| 6603142 | Antifuse incorporating tantalum nitride barrier layer A metal-to-metal antifuse disposed above and insulated from a semiconductor substrate comprises a first metal layer disposed above and insulated from the semiconductor substrate. A layer of antifuse material is disposed over and in electrical contact with... | 08/05/2003 |
| 6570798 | Antifuse memory cell and antifuse memory cell array An antifuse memory cell comprises a first antifuse having a first electrode and a second electrode, a second antifuse having a first electrode and a second electrode, and an MOS transistor having a gate, a source and a drain, wherein the first electrode o... | 05/27/2003 |
| 6570805 | Antifuse memory cell and antifuse memory cell array An antifuse memory cell comprises a first antifuse having a first electrode and a second electrode, a second antifuse having a first electrode and a second electrode, and an MOS transistor having a gate, a source and a drain, wherein the first electrode o... | 05/27/2003 |
| 6567968 | Block level routing architecture in a field programmable gate array An FPGA architecture has top, middle and low levels. The top level of the architecture is an array of the B16×16 tiles arranged in a rectangular array and enclosed by I/O blocks on the periphery. On each of the four sides of a B16×16 tile, and also asso... | 05/20/2003 |
| 6560743 | Cyclic redundancy checking of a field programmable gate array having a SRAM memory architecture A method for detecting an error in data stored in configuration SRAM and user assignable SRAM in a FPGA comprises the steps of providing a serial data stream into the FPGA from an external source, loading data from the serial data stream into the configur... | 05/06/2003 |
| 6549035 | High density antifuse based partitioned FPGA architecture An antifuse based FPGA architecture is partitioned into repeatable blocks of logic modules to reduce the programming time of the array and to minimize parasitic capacitance and current leakage in the array. With repeatable blocks the size of the FPGA may ... | 04/15/2003 |
| 6531891 | Method and apparatus of memory clearing with monitoring memory cells A field-programmable gate array (FPGA) comprising an array of RAM memory cells comprising at least one row of RAM memory cells, each RAM cell of the at least one row of RAM memory cells coupled to a row driver line; a row decoder coupled to a first end of... | 03/11/2003 |
| 6529038 | Antifuse programming method A method for programming antifuses includes applying a programming pulse having a magnitude equal to the programming potential across the conductive electrodes of the antifuse such that the more positive potential is applied to the upper electrode of the ... | 03/04/2003 |
| 6518824 | Antifuse programmable resistor A user-programmable resistor module includes a resistive element connected in series with first and second antifuses between an input circuit node and an output circuit node. Third and fourth antifuses are connected in series between the input circuit nod... | 02/11/2003 |
| 6504398 | Integrated circuit that includes a field-programmable gate array and a hard gate array having the same underlying structure An integrated circuit (IC) includes both a field-programmable gate array (FPGA) and a hard array (HA). The FPGA includes a first set of functional groups that each include an underlying logic structure and memory cells for programming the underlying logic... | 01/07/2003 |
| 6496887 | SRAM bus architecture and interconnect to an FPGA An SRAM bus architecture includes pass-through interconnect conductors. Each of the pass-through interconnect conductors is connected to routing channels of the general interconnect architecture of the FPGA through an element which includes a pass transis... | 12/17/2002 |
| 6492206 | Antifuse with improved radiation SEDR A metal-to-metal antifuse according to the present invention is disposed between a lower conductive electrode and an upper conductive electrode. The conductive electrodes may comprise either a barrier metal or a tungsten plug, and are each in electrical c... | 12/10/2002 |
| 6476636 | Tileable field-programmable gate array architecture An apparatus includes a field-programmable gate array (FPGA). The FPGA includes a first FPGA tile, and the first FPGA tile includes a plurality of functional groups (FGs), a regular routing structure, and a plurality of interface groups (IGs). The plurali... | 11/05/2002 |
| 6446242 | Method and apparatus for storing a validation number in a field-programmable gate array An apparatus including a field-programmable gate array (FPGA) where the FPGA includes a plurality of X signal lines, a plurality of Y signal lines, and a plurality of memory cells. A first set of the memory cells are used to implement programmable interco... | 09/03/2002 |
| 6437365 | Raised tungsten plug antifuse and fabrication processes An antifuse comprises a lower electrode formed from a metal layer in a microcircuit. A interlayer dielectric layer is disposed over the lower electrode and has an aperture formed therein. A conductive plug, formed from a material such as tungsten, is form... | 08/20/2002 |
| 6430088 | Embedded static random access memory for field programmable gate array A dual ported (simultaneous read/write) SRAM block with an additional load port that interacts with the circuitry employed in the loading and testing of the configuration data of the FPGA core is disclosed. Each SRAM block contains circuits in both the re... | 08/06/2002 |
| 6392437 | Programmable multi-standard I/O architecture for FPGAs The invention discloses an architecture for the input/output buffer section of an FPGA. It provides a convenient and efficient addressing scheme for addressing fuse matrices that are used to configure programmable input/output buffers in the FPGA. The pro... | 05/21/2002 |
| 6362649 | Field programmable gate array with mask programmed input and output buffers A hybrid integrated circuit architecture comprising a mask programmable portion and a field programmable gate array portion. The mask programmable portion has a plurality of mask programmed input and output buffer circuits, and a first group of input/outp... | 03/26/2002 |
| 6356478 | Flash based control for field programmable gate array A circuit for controlling a switching transistor in a reprogrammable FPGA device comprises first and second floating gate flash memory transistors. A first floating gate flash memory transistor has a drain electrically coupled to a first voltage potential... | 03/12/2002 |
| 6324102 | Radiation tolerant flash FPGA A radiation tolerant flash memory cell switch includes a programming transistor switch coupled between two circuit nodes to be selectively connected to one another. A floating gate flash memory switch control circuit has a switch-control node coupled to t... | 11/27/2001 |
| 6301696 | Final design method of a programmable logic device that is based on an initial design that consists of a partial underlying physical template A method of making an integrated circuit (IC) includes establishing an initial design for a field-programmable gate array (FPGA) to be included in the IC that includes programmable connections that can be programmed to implement a desired function; establ... | 10/09/2001 |
| 6285212 | Block connector splitting in logic block of a field programmable gate array An FPGA architecture has top, middle and low levels. The top level of the architecture is an array of the B16×16 tiles arranged in a rectangular array and enclosed by I/O blocks on the periphery. On each of the four sides of a B16×16 tile, and also asso... | 09/04/2001 |
| 6272655 | Method of reducing test time for NVM cell-based FPGA The present invention provides for a method of testing an FPGA using NVM memory cells for programmable interconnects. The NVM memory cells are arranged as a memory array of rows and columns. User-configurable logic elements and interconnections, which are... | 08/07/2001 |
| 6252273 | Nonvolatile reprogrammable interconnect cell with FN tunneling device for programming and erase A programmable interconnect cell for selectively connecting circuit nodes of a field programmable integrated circuit array in a semiconductor substrate includes a switch field effect transistor, a sense field effect transistor, and an electron tunneling d... | 06/26/2001 |
| 6237124 | Methods for errors checking the configuration SRAM and user assignable SRAM data in a field programmable gate array A method for detecting an error in data stored in configuration SRAM and user assignable SRAM in a FPGA comprises the steps of providing a serial data stream into the FPGA from an external source, loading data from the serial data stream into the configur... | 05/22/2001 |
| 6160420 | Programmable interconnect architecture A user-programmable interconnect architecture, which may be used for logic arrays for digital and analog system design, is disclosed. In one embodiment, a plurality of logic cells or modules in a matrix are connected by vertical and horizontal wiring chan... | 12/12/2000 |
| 6150837 | Enhanced field programmable gate array An enhanced performance field programmable gate array integrated circuit comprises a field programmable gate array and other functional circuitry such as a mask-programmable gate array in the same integrated circuit. A circuit interface provides communica... | 11/21/2000 |
| 6150705 | Dielectric-polysilicon-dielectric-polysilicon-dielectric antifuse for field programmable logic application A novel antifuse structure includes a novel antifuse material layer comprises a first dielectric layer, a first polysilicon layer (which may optionally be lightly doped) disposed over the first dielectric layer, and a second dielectric layer disposed over... | 11/21/2000 |
| 6124193 | Raised tungsten plug antifuse and fabrication processes An antifuse comprises a lower electrode formed from a metal layer in a microcircuit. A interlayer dielectric layer is disposed over the lower electrode and has an aperture formed therein. A conductive plug, formed from a material such as tungsten, is form... | 09/26/2000 |
| 6111302 | Antifuse structure suitable for VLSI application The present invention relates to a high performance, high reliability antifuse using conductive electrodes. The problem of switch-off of the programmed antifuses is solved by reducing the thermal conductivity of the conductive electrodes. This is achieved... | 08/29/2000 |
| 6049487 | Embedded static random access memory for field programmable gate array A dual ported (simultaneous read/write) SRAM block with an additional load port that interacts with the circuitry employed in the loading and testing of the configuration data of the FPGA core is disclosed. Each SRAM block contains circuits in both the re... | 04/11/2000 |
| 6038627 | SRAM bus architecture and interconnect to an FPGA An SRAM bus architecture includes pass-through interconnect conductors. Each of the pass-through interconnect conductors is connected to routing channels of the general interconnect architecture of the FPGA through an element which includes a pass transis... | 03/14/2000 |
