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| Number | Title | Issue Date |
| 7711055 | System and method for signal alignment when communicating signals A method and system are provided for aligning signals in a communication system. The method and system include alignment logic or functionality configured to compensate for signal propagation discrepancies when communicating signals between one or more other devices... | 05/04/2010 |
| 7689748 | Event handler for context-switchable and non-context-switchable processing tasks Embodiments of a system and method for handling interrupts are described herein. In an embodiment interrupts from various client components in a system (also referred to as clients) are processed by an interrupt handler component uniformly. The various clients signa... | 03/30/2010 |
| 7688925 | Bit-deskewing IO method and system An IO method and system for bit-deskewing are described. Embodiment includes a computer system with multiple components that transfer data among them. In one embodiment, a system component receives a forward strobe signal and multiple data bit signals from a transmi... | 03/30/2010 |
| 7668269 | Systems, methods, and apparatus for phase noise mitigation A method of signal processing according to an embodiment includes estimating a response of a transmission channel during a symbol period. Based on an estimated response of the transmission channel, components of a model of a phase noise process during the symbol per... | 02/23/2010 |
| 7663701 | Systems, methods, and apparatus for noise reduction Systems, methods, and apparatus for noise reduction include noise estimation from blanking interval information. Such systems, methods, and apparatus may also include temporal filtering, scene change detection, inverse telecine, and/or DC preservation. ... | 02/16/2010 |
| 7663635 | Multiple video processor unit (VPU) memory mapping A system and method for memory mapping in a multiple video processor (multi VPU) system is described. In various embodiments, rendering tasks are shared among multiple VPUs in parallel to provide improved performance and capability with minimal increased cost. In va... | 02/16/2010 |
| 7649537 | Dynamic load balancing in multiple video processing unit (VPU) systems Systems and methods are provided for processing data. The systems and methods include multiple processors that each couple to receive commands and data, where the commands and/or data correspond to frames of video that include multiple pixels. An interlink module is... | 01/19/2010 |
| 7613346 | Compositing in multiple video processing unit (VPU) systems Systems and methods are provided for processing data. The systems and methods include multiple processors that each couple to receive commands and data, where the commands and/or data correspond to frames of video that include multiple pixels. Additionally, an inter... | 11/03/2009 |
| 7583755 | Systems, methods, and apparatus for mitigation of nonlinear distortion A method among the embodiments includes calculating a value of a parameter of a nonlinear model of a signal as transmitted into a transmission channel, and applying the calculated value to obtain an estimate of data values carried by the signal. Applications to mult... | 09/01/2009 |
| 7509515 | Method and system for communicated client phase information during an idle period of a data bus A system and method for transmitting client phase information to a host device over a bidirectional data link is described. Embodiments include detecting a phase of a clock signal relative to a data signal transmitted between a host device and a client device over a... | 03/24/2009 |
| 7487378 | Asymmetrical IO method and system An asymmetrical IO method and system are described. In one embodiment, a host device includes shared resources for data synchronization of the host device and a client device. The shared resources include a shared phase interpolator. In an embodiment, data lines bet... | 02/03/2009 |
| 7447869 | Method and apparatus for fragment processing in a virtual memory system A method and apparatus for fragment processing in a virtual memory system are described. Embodiments of the invention include a coprocessor comprising a virtual memory system for accessing a physical memory. Page table logic and fragment processing logic scan a page... | 11/04/2008 |
| 7343512 | Controlling clock rates of an integrated circuit including generating a clock rate control parameter from integrated circuit configuration Systems and methods for controlling clock rates of circuits are provided. The systems and methods, collectively referred to as clock rate control, generate a clock rate control parameter from data of one or more fuses. The clock rate control detects any overclocked ... | 03/11/2008 |
| 7239322 | Multi-thread graphic processing system The present invention includes a multi-thread graphics processing system and method thereof including a reservation station having a plurality of command threads stored therein. The system and method further includes an arbiter operably coupled to the reservation st... | 07/03/2007 |
| 7215022 | Multi-die module A multi-die module is electrically connected to both an unpackaged die and a packaged die as disclosed herein. The multi-die module has a footprint that is the same as conventional multi-die packages, which do not include packaged die, thereby allowing the multi-die... | 05/08/2007 |
| 7187415 | System for detecting aspect ratio and method thereof Video is received at a standard aspect ratio. The video includes video content having an alternate aspect ratio. The video content is provided in a letterboxed format with black bars to make up the standard aspect ratio. The video is analyzed to identify portions of... | 03/06/2007 |
| 7123266 | Method and apparatus for a video graphics circuit having parallel pixel processing A method and apparatus for parallel processing of pixel information within a video graphics circuit is accomplished when the video graphics circuit includes a set-up engine, an edgewalker circuit, a span processing circuit, and a plurality of pixel processing circui... | 10/17/2006 |
| 7112884 | Integrated circuit having memory disposed thereon and method of making thereof An integrated circuit having memory disposed thereon and method of making thereof includes a standard dimension carrier substrate and an information router integrated on the carrier substrate. Further included therein is at least one system memory integrated on the ... | 09/26/2006 |
| 7111156 | Method and apparatus for multi-thread accumulation buffering in a computation engine A method and apparatus for enhancing flexibility of instruction ordering in a multi-thread processing system that performs multiply and accumulate operations is presented. A plurality of accumulation registers is provided for storing the results of an adder, wherein... | 09/19/2006 |
| 7109987 | Method and apparatus for dual pass adaptive tessellation A method and apparatus for dual pass adaptive tessellation includes a vertex grouper tessellator operably coupled to receive primitive information and an index list and a shader processing unit coupled to the vertex grouper tessellator. During a first pass, the shad... | 09/19/2006 |
| 7109992 | Apparatus for generating efficient wide-line ends A graphics processing circuit includes a line end generation circuit operative to generate line aligned end cap data in response to primitive data; and a rasterizer, coupled to the line end generation circuit, operative to generate pixel data representing a line to ... | 09/19/2006 |
| 7103226 | Video processor with composite graphics and video picture elements A video processor integrates the processing of video and graphics data by restructuring the discrete blocks of luminance and chrominance component data associated with video image data (Y,U,V) into composite pixel values (YUYV), and performing the subsequent process... | 09/05/2006 |
| 7091971 | System, method, and apparatus for multi-level hierarchical Z buffering A secondary representative Z value memory includes a reduced-resolution representation of a primary representative Z value memory. Upon updating of a block of the primary representative Z value memory, one or more corresponding values are calculated for updating the... | 08/15/2006 |
| 7075542 | Selectable multi-performance configuration The present invention relates to a selectable multi-performance configuration. Instead of the traditional methods of producing separate high-end and low-end graphics chips, the present invention produces processing systems in a single unit. The single unit is readil... | 07/11/2006 |
| 7061495 | Method and apparatus for rasterizer interpolation The present invention relates to a rasterizer interpolator. In one embodiment, a setup unit is used to distribute graphics primitive instructions to multiple parallel rasterizers. To increase efficiency, the setup unit calculates the polygon data and checks it again... | 06/13/2006 |
| 7057620 | Method and apparatus for graphics rendering on a mobile device A method and apparatus for graphics rendered in a mobile device includes a command queue capable of receiving a plurality of rendering commands, a generate_event command and a wait_until command. The wait_until command corresponds to the completion of a specific ope... | 06/06/2006 |
| 7015930 | Method and apparatus for interpolating pixel parameters based on a plurality of vertex values A method and apparatus for interpolating pixel parameters based on the plurality of vertex values includes operating first and a setup mode and a calculation mode. The method and apparatus includes, while in a setup mode, generating a plurality of differential geome... | 03/21/2006 |
| RE39003 | Closed caption support with timewarp Method of providing closed captioned data to a television viewer comprised of detecting closed captioned data signals transmitted in conjunction with a television signal, decoding the data signals to caption display signals, and displaying the caption display signal... | 03/07/2006 |
| 7002899 | Method and apparatus to improve SCDMA headroom A method of determining when cable modems in a distributed digital data delivery service over cable TV hybrid fiber coaxial cable network have a headroom problem and resolving said problem. The method involves measuring the burst power from each cable modem, and if ... | 02/21/2006 |
| 6999098 | Apparatus for converting floating point values to gamma corrected fixed point values Graphics processing circuitry includes processing circuitry operative to generate pixel information in response to primitive information, and a correction circuit, coupled to the processing circuitry, operative to generate gamma corrected pixel information in respon... | 02/14/2006 |
| 6975325 | Method and apparatus for graphics processing using state and shader management A method and apparatus for graphics processing using state and shader management includes at least one state and shader cache coupled to a compiler for compiling a hardware state and shader vector from an abstract state vector. Also included is an abstract state vec... | 12/13/2005 |
| 6950105 | Power consumption management in a video graphics accelerator A method and apparatus matches one or more clock speeds used in, or used by, a graphics accelerator so as to match graphics processing requirements to the speed of the clock source or sources. Clock speed is adjusted under software control to match current requireme... | 09/27/2005 |
| 6940517 | Apparatus and method for pixel conversion using multiple buffers A method and apparatus for pixel conversion using multiple buffers includes receiving a position value including a horizontal value and a vertical value. The method and apparatus further includes receiving a byte per pixel value and a pixels per group. The method an... | 09/06/2005 |
| 6919908 | Method and apparatus for graphics processing in a handheld device The present invention includes a method and apparatus for graphics processing in a handheld device including a transform engine capable of receiving vertex information. The transform engine generates a plurality of vertices from the vertex information, wherein each ... | 07/19/2005 |
| 6891410 | Method and apparatus for determining a processing speed of an integrated circuit A method and apparatus for determining a processing speed of an integrated circuit includes a first flip flop having an input port receiving an input signal, an output port providing a flip flop output signal and a timing port receiving an incoming clock signal. The... | 05/10/2005 |
| 6870892 | Diversity receiver with joint baud clock recovery First and second RF signals in the respective first and second channels of a multiple channel diversity receiver are processed jointly in a joint timing loop filter for baud clock recovery. The channel with the stronger signal determines the frequency of the baud cl... | 03/22/2005 |
| 6826095 | Method and apparatus for data inversion in memory device A method of writing information to a synchronous memory device by examining a present word of N bits to be written, where each bit has a high or low value. The present word is compared to a previous word also having N bits to identify the number of bit transitions f... | 11/30/2004 |
| 6810470 | Memory request interlock A memory controller for use in a computer system. The controller has a buffer having an input configured to receive read and write requests. Each request has an associated memory address. For a selected received request, prior received requests out of a set of the r... | 10/26/2004 |
| 6804266 | Method and apparatus for handling private data from transport stream packets In accordance with a specific aspect of the present invention, a compressed video stream, such as an MPEG-2 video stream, is received by a transport demultiplexor, synchronized, parsed into separate packet types, and written to buffer locations external the demultip... | 10/12/2004 |
| 6798667 | Solder ball collapse control apparatus and method thereof A solder ball collapse control apparatus and method thereof includes a plurality of first solder members, pieces of solder material in a shape capable of being used to properly create a solder joint. The first solder members have a first solder dimension and a first... | 09/28/2004 |
