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| Number | Title | Issue Date |
| 8143111 | System and method for configuring an integrated circuit A system and method for configuring an integrated circuit. Embodiments include a method for manufacturing an integrated circuit (IC), comprising associating configuration items of the integrated circuit with at least one fuse of at least one type of fuse, wherein a ... | 03/27/2012 |
| 8130323 | Closed loop DAC calibration A video signal processing system including a digital signal processing (DSP) module, a digital offset module coupled to the DSP module, a gain module, and a digital to analog converter (DAC) coupled to the DSP module and to the gain module, wherein the DAC is config... | 03/06/2012 |
| 8103131 | Compositing in multiple video processing unit (VPU) systems Systems and methods are provided for processing data. The systems and methods include multiple processors that each couple to receive commands and data, where the commands and/or data correspond to frames of video that include multiple pixels. Additionally, an inter... | 01/24/2012 |
| 8065614 | System for displaying video and method thereof A system and method for providing playback of multiple video streams simultaneously is shown and described. A priority is assigned to individual windows of a plurality of windows used for playback of the video streams. A current window being accessed by a user is as... | 11/22/2011 |
| 8054900 | Symmetrical data signal processing In a digital communications receiver configured to receive, via a communications channel, a received first signal representing a sequence of symbols, each symbol being encoded to be representative of data bits, a method of processing the received signal includes adj... | 11/08/2011 |
| 8054314 | Applying non-homogeneous properties to multiple video processing units (VPUs) A system and method for applying non-homogeneous properties to multiple video processing units (VPUs) in a multiple VPU system are described. Respective VPUs in the system cooperate to produce a frame to be displayed. In various embodiments, data output by different... | 11/08/2011 |
| 7970956 | Graphics-processing system and method of broadcasting write requests to multiple graphics devices Described are a system and method for broadcasting write requests to a plurality of graphics devices. A different address range of graphics device addresses is associated with each graphics device of the plurality of graphics devices. A controller receives a write r... | 06/28/2011 |
| 7969512 | Memory bandwidth amortization A system for processing video information, the system including a memory configured to store video information, a memory controller coupled to the memory and configured to receive memory requests for the video information, a first video signal processing client coup... | 06/28/2011 |
| 7869525 | Dynamic bus inversion method and system A dynamic bus inversion (DBI) method and system are described. In various embodiments, a transmitter transmits data over a multi-bit high-speed bus to a receiver. In an embodiment, the transmitter determines whether to invert the bus based on the number of data bits... | 01/11/2011 |
| 7834935 | SCART fast blanking signal processing A video receiver for SCART input includes an input configured to receive a composite video signal, RGB signals, and a switch-indicating signal, a first digitizer module coupled to the input and including a one-bit slicer configured to receive and convert the switch-... | 11/16/2010 |
| 7733422 | Rapid channel signal identification An apparatus, for use in a receiver configured to receive electronic signals, for identifying digital signals that are available for reception, includes a timing recovery device configured to receive an incoming signal, related to a transmitted signal, the incoming ... | 06/08/2010 |
| 7698493 | Methods and apparatus for translating write request messages in a computing system Methods and apparatus are disclosed to translate memory write requests to be transmitted from a first processor to a second processor in a computing system, such as between a CPU and a Southbridge, as an example. A method includes generating a memory write request i... | 04/13/2010 |
| 7657762 | Apparatus and methods for power management of a circuit module The present disclosure relates to methods and apparatus for controlling power consumption of a plug-in card or circuit module. The disclosed method, in particular, controls power to a circuit module and includes implementing a user interface and power manager to aut... | 02/02/2010 |
| 7656416 | Apparatus for generating anti-aliased and stippled 3d lines, points and surfaces using multi-dimensional procedural texture coordinates A graphics processing circuit includes an anti-aliasing and stippling circuit operative to provide a primitive texture coordinate set in response to vertex data, the anti-aliasing and stippling circuit performing anti-aliasing operations, in parallel, with at least ... | 02/02/2010 |
| 7636095 | Pixel delta interpolation method and apparatus A method for rendering an object including receiving a pixel tile representing a portion of a primitive to be rendered, determining attributes of a reference pixel within the pixel tile, and determining the attributes of neighboring pixels within the pixel tile base... | 12/22/2009 |
| 7633549 | Apparatus and method for image rendering An apparatus and method for image rendering includes a first buffer operative to receive first video data. A motion mad updater receives video data from the first buffer and updates a motion map using the first video data. A grain information generator is coupled to... | 12/15/2009 |
| 7624123 | Image processing system and method An image processing system and method receives one or more digital images in the form of image data, including selected object data of a digital image, and determines, by an electronic recognition process, if a recognition match is available between the selected obj... | 11/24/2009 |
| 7594069 | Method and apparatus for single instruction multiple data caching An apparatus and method for single instruction multiple data caching includes a memory access request generator operative to receive a primary access request. The method and apparatus further includes a cache controller coupled to the memory access request generator... | 09/22/2009 |
| 7573531 | Rapid channel signal identification An apparatus, for use in a receiver configured to receive electronic signals, for identifying digital signals that are available for reception, includes a timing recovery device configured to receive an incoming signal, related to a transmitted signal, the incoming ... | 08/11/2009 |
| 7558337 | Systems, methods, and apparatus for impulse noise mitigation A method of signal processing according to one of several embodiments includes estimating a deterministic component of a received signal. The estimating is based on an estimated response of a transmission channel. Based on the estimated deterministic component, a no... | 07/07/2009 |
| 7551679 | Symmetrical data signal processing In a digital communications receiver configured to receive, via a communications channel, a received first signal representing a sequence of symbols, each symbol being encoded to be representative of data bits, a method of processing the received signal includes adj... | 06/23/2009 |
| 7551177 | Methods and apparatus for retrieving and combining samples of graphics information Disclosed are methods and apparatus for accomplishing the fetching or sampling of channels of pixels or texels such as neighboring pixels or texels or non-neighboring pixels or texels in a simultaneous operation in order to achieve optimization of the performance of... | 06/23/2009 |
| 7495477 | Apparatus and methods for self-biasing differential signaling circuitry having multimode output configurations for low voltage applications The present disclosure relates to a differential signaling circuit including differential signaling circuitry having at least one output and one input, that can operate in multiple mode of operations while using a single, low voltage supply source. Two or more switc... | 02/24/2009 |
| 7486297 | Method and apparatus for image processing in a handheld device The present invention provides a method and apparatus for image processing using a graphics processor in a handheld device including a first memory device receiving a video input signal containing encoded video frame having a plurality of portions of encoded video f... | 02/03/2009 |
| D579880 | Domino-mahjong style connector | 11/04/2008 |
| 7440677 | Detection of copy protection indicators or redistribution control indicators in an analog video signal To detect at least one of a copy protection indicator and a redistribution control indicator in an analog video signal, the video format of the analog video signal is determined, e.g., by detecting the horizontal frequency and vertical frequency of the signal. Based... | 10/21/2008 |
| 7434034 | SIMD processor executing min/max instructions The result of eight find_min_16 of lookup-min_16, find_max_l6x, lookup_max_16 instructions may be stored in memory storage units of operand storage 24, using SIMD at addressing techniques detailed in U.S. patent application Ser. No. 10/929,992, filed Aug. 30,... | 10/07/2008 |
| 7427990 | Data replacement method and circuit for motion prediction cache A system for decoding a video bitstream and a method for replacing image data in a motion prediction cache are described. For each of the cache lines, a tag distance between pixels stored in the cache line and uncached pixels that are to be stored in the cache is ca... | 09/23/2008 |
| 7423644 | Method and apparatus for dual pass adaptive tessellation A method and apparatus for dual pass adaptive tessellation includes a vertex grouper tessellator operably coupled to receive primitive information and an index list and a shader processing unit coupled to the vertex grouper tessellator. During a first pass, the shad... | 09/09/2008 |
| D574778 | Domino-mahjong style connector | 08/12/2008 |
| 7394500 | World wide analog television signal receiver A TV signal reception system is configured to include adjustable components and a controller to provide instructions to adjust the adjustable components. By pre-arranging configurations corresponding to multiple variants of world wide TV standards, the TV signal rec... | 07/01/2008 |
| 7392411 | Systems and methods for dynamic voltage scaling of communication bus to provide bandwidth based on whether an application is active Systems and methods for dynamic power management of electronic devices are disclosed. In one form, a system employing dynamic power management for electronic devices includes a central processing unit operable to process information via a communication bus. The syst... | 06/24/2008 |
| 7386410 | Closed loop controlled reference voltage calibration circuit and method A variable reference voltage circuit controllable in closed loop, for calibrating off-chip and on-chip drivers, margining and optimizing a reference voltage, for interfaces such as DDR2 or any other suitable interface. In one example, the on-chip variable reference ... | 06/10/2008 |
| 7385545 | Reduced component digital to analog decoder and method An n bit D/A decoder is formed using P-type and N-type transistor switches, instead of convention CMOS switches. Each P-type and N-type switch may be formed of fewer transistors than those used to form a CMOS switch, thereby reducing the overall transistor count. Th... | 06/10/2008 |
| 7385534 | Methods and apparatus for processing variable length coded data An apparatus for processing variable length coded data includes a coefficient buffer unit and several lookup tables. The coefficient buffer unit includes a coefficient memory and an index register for storing an indication of a non-zero nature of coefficients stored... | 06/10/2008 |
| 7376692 | Method and system for receiving and framing packetized data In accordance with a specific aspect of the present invention, a compressed video stream, such as an MPEG-2 video stream, is received by a transport demultiplexor, synchronized, parsed into separate packet types, and written to buffer locations external the demultip... | 05/20/2008 |
| 7362583 | Thermal management device for multiple heat producing devices A thermal management device for a circuit substrate having at least a first heat generating component and at least a second heat generating component, the thermal management device includes a first thermal spreader and a second thermal spreader. The second thermal s... | 04/22/2008 |
| 7356823 | Method for displaying single monitor applications on multiple monitors driven by a personal computer A direct access driver solves limitations of DirectX operation under the Microsoft architecture when using multiple monitors. The direct access driver allows applications employing DirectX application program interfaces to use hardware acceleration without display e... | 04/08/2008 |
| 7345510 | Method and apparatus for generating a reference signal and generating a scaled output signal based on an input signal An input signal is routed to a first logic one reference signal generator or alternatively routed to a second logic one reference signal generator based at least one a voltage level of the input signal. When the voltage level of the input signal is less than a thres... | 03/18/2008 |
| 7343508 | Dynamic clock control circuit for graphics engine clock and memory clock and method A variable clock control information generator receives graphics engine activity data relating to the operating level of a graphics engine, and memory activity data relating to an activity level of memory. In response, the variable clock control information generato... | 03/11/2008 |
