Celebrity Inventors
Glam girl Heddy Lamar may have used her good looks to good effect on the silver screen, but she put her smarts to better use as an inventor. During World War II, she co-patented a frequency-switching system for torpedo guidance that was considered years ahead of its time.
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| Number | Title | Issue Date |
| 7962664 | Techniques for generating a trace stream for a data processing apparatus Trace circuitry, and a method of operating such trace circuitry, are provided for generating a trace stream indicative of activities of monitored circuitry of a data processing apparatus. The monitored circuitry produces data elements indicative of those activities,... | 06/14/2011 |
| 7960759 | Integrated circuit layout pattern for cross-coupled circuits A circuit 32 is provided comprising a first diffusion region 34 and a parallel second diffusion region 36. A sequence of N gate layers 40, 42, 46 is provided with a first and an Nth of these gate layers covering different respective ones ... | 06/14/2011 |
| 7949914 | Diagnostic mode switching A system is described having a JTAG diagnostic unit and a serial wire diagnostic unit. A watcher unit is connected to a data connection shared between the diagnostic units. Special patterns detected upon the shared data connection serve to switch between diagnostic ... | 05/24/2011 |
| 7949848 | Data processing apparatus, method and computer program product for reducing memory usage of an object oriented program The present invention for reducing memory usage of an object oriented program. The object oriented program comprises class definitions used to create objects, each class definition providing at least one function that can be run in respect of objects created from th... | 05/24/2011 |
| 7949835 | Data processing apparatus and method for controlling access to memory A data processing apparatus and method are provided for controlling access to memory. The data processing apparatus comprises main processing logic operable to execute a sequence of instructions in order to perform a process, and subsidiary processing logic operable... | 05/24/2011 |
| 7948816 | Accessing data within a memory formed of memory banks A memory is disclosed that comprises: an input for receiving an input signal and an output for outputting data; a plurality of data storage cells for storing individual units of data; said plurality of data storage cells being arranged in an array; a plurality of sa... | 05/24/2011 |
| 7945811 | Low power, high reliability specific compound functional units To prevent short path errors from occurring in systems having error detection and recovery mechanisms, functional elements are combined to form compound functional units comprising at least two evaluation stages, each evaluation stage including at least one function... | 05/17/2011 |
| 7945806 | Data processing apparatus and method for controlling a transfer of payload data over a communication channel A data processing apparatus has initiator circuitry for initiating a transfer of payload data in a first clock cycle, and recipient circuitry for receiving the payload data in a later clock cycle. A communication channel carries the payload data along with associate... | 05/17/2011 |
| 7945607 | Data processing apparatus and method for converting a number between fixed-point and floating-point representations A data processing apparatus and method are provided for converting a number between fixed-point and floating-point representations. More particularly, the data processing apparatus comprises a data processing unit operable to execute instructions, with the data proc... | 05/17/2011 |
| 7941608 | Cache eviction A method and data processing apparatus comprise a cache having a plurality of data entries; an eviction buffer comprising an information portion and a data portion; and eviction logic to transfer information associated with a first of the plurality of data entries f... | 05/10/2011 |
| 7941584 | Data processing apparatus and method for performing hazard detection A data processing apparatus and method are provided for performing hazard detection in a series of access requests issued by processing circuitry for handling by one or more slaves. The requests include one or more write access requests to be performec by an address... | 05/10/2011 |
| 7940546 | ROM array A ROM array is provided, comprising a plurality of columns of memory cells, wherein each column of memory cells is coupled to a shared bit line which is shared by that column of memory cells and an adjacent column of memory cells. Each column of memory cells has its... | 05/10/2011 |
| 7937626 | Techniques for generating a trace stream for a data processing apparatus A data processing apparatus and method are provided for generating a trace stream. The data processing apparatus comprises logic for producing data elements, and trace logic for producing a stream of trace elements representative of at least some of the data element... | 05/03/2011 |
| 7937535 | Managing cache coherency in a data processing apparatus Each of plural processing units has a cache, and each cache has indication circuitry containing segment filtering data. The indication circuitry responds to an address specified by an access request from an associated processing unit to reference the segment filteri... | 05/03/2011 |
| 7936578 | Read only memory cell for storing a multiple bit value A read only memory cell for storing a multiple bit value is disclosed. The read only memory cell comprises: at least three output lines, each of the at least three output lines representing a different multiple bit value; a switching device connected between a singl... | 05/03/2011 |
| 7936290 | Dynamic selection of suitable codes for variable length coding and decoding A data compressor for compressing a data signal and a corresponding data decompressor are disclosed. The data compressor comprises: compression circuitry for compressing said data signal using a plurality of variable length compression codes; a digital code select s... | 05/03/2011 |
| 7934029 | Data transfer between devices within an integrated circuit An integrated circuit 2 is provided including multiple devices 4, 6, 8, 10, 12, 14 for communicating via an interconnect 16. A sending device 18 includes a sideband signal indicating the use of a representation of a repeating data word in... | 04/26/2011 |
| 7930526 | Compare and branch mechanism A data processing system is provided that includes an instruction decoder 20 responsive to a compare and branch instruction CHKA.X that performs a comparison between first and second values stored in first and second registers Rn, Rm respectively. A target br... | 04/19/2011 |
| 7926021 | Insertion of error detection circuits based on error propagation within integrated circuits A method of selecting where error detection circuits should be placed within an integrated circuit uses simulation of a reference and test design with errors injected into the test design and then fan out analysis performed upon those injected errors to identify err... | 04/12/2011 |
| 7925871 | Identification and correction of cyclically recurring errors in one or more branch predictors A data processing apparatus 2 is provided with one or more branch predictors 10 for generating branch predictions. A supervising predictor 12 is responsive to at least a stream of branch predictions to identify one or more cyclically recurring e... | 04/12/2011 |
| 7925868 | Suppressing register renaming for conditional instructions predicted as not executed Within a data processing system including a register renaming mechanism, register renaming for some conditional instructions which are predicted as not-executed is suppressed. The conditional instructions which are subject to such suppression of renaming may not be ... | 04/12/2011 |
| 7925867 | Pre-decode checking for pre-decoded instructions that cross cache line boundaries A data processing and method are provided for pre-decoding instructions. The data processing apparatus has pre-decoding circuitry for receiving instructions fetched from a memory and for performing a pre-decoding operation to generate corresponding pre-decoded instr... | 04/12/2011 |
| 7925866 | Data processing apparatus and method for handling instructions to be executed by processing circuitry A data processing apparatus and method are provided for handling instructions to be executed by processing circuitry. The processing circuitry has a plurality of processor states, each processor state having a different instruction set associated therewith. Pre-deco... | 04/12/2011 |
| 7925840 | Data processing apparatus and method for managing snoop operations The present invention provides a data processing apparatus and method for managing snoop operations. The data processing apparatus has a plurality of processing units for performing data processing operations requiring access to data in shared memory, with at least ... | 04/12/2011 |
| 7925836 | Selective coherency control A data processing system is provided with a general purpose programmable processor and an accelerator processor. Coherency control circuitry manages data coherence between data items which may be stored within a cache memory and/or a further memory. Memory access re... | 04/12/2011 |
| 7924858 | Use of a data engine within a data processing apparatus A data processing apparatus and method of operation of such a data processing apparatus are disclosed. The data processing apparatus has a main processing unit operable to perform a plurality of data processing tasks, and a data engine for performing a number of tho... | 04/12/2011 |
| 7924638 | Redundancy architecture for an integrated circuit memory An integrated circuit memory is described having multiple memory banks which are grouped into repair groups Group0, Group1. One of the memory banks is provided with redundant rows which can be used to substitute for a defective row found within any of ... | 04/12/2011 |
| 7924056 | Low voltage differential signalling driver A low voltage differential signalling driver is provided in which a first output node and a second output node provide a differential signal. First differential steering switch circuitry is switched in dependence on a differential input signal to selectively connect... | 04/12/2011 |
| 7920584 | Data processing system A data processing system is provided comprising a main processor operable to perform a plurality of data processing tasks, a data engine having a data engine core operable to perform a number of said plurality of data processing tasks on behalf of said main processo... | 04/05/2011 |
| 7920411 | Converting SRAM cells to ROM cells A method of converting a static random access memory cell to a read only memory cell and the cell thus converted is disclosed. The cell to be converted comprises a data retention portion powered by a higher and lower voltage supply line and four transistors arranged... | 04/05/2011 |
| 7917735 | Data processing apparatus and method for pre-decoding instructions A data processing apparatus and method are provided for pre-decoding instructions. The data processing apparatus has pre-decoding circuitry for receiving instructions fetched from memory and for performing a pre-decoding operation to generate corresponding pre-decod... | 03/29/2011 |
| 7917701 | Cache circuitry, data processing apparatus and method for prefetching data by selecting one of a first prefetch linefill operation and a second prefetch linefill operation Prefetch circuitry is provided which is responsive to a determination that the memory address of a data value specified by a current access request is the same as a predicted memory address, to perform either a first prefetch linefill operation or a second prefetch ... | 03/29/2011 |
| 7913131 | Scan chain cell with delay testing capability A scan chain cell 24 is provided with a built-in delay testing capability. An inverter 32 generates an inverted form of the cell output which is available within the scan chain cell 24 for rapid use in forming a transition at the cell output Q. ... | 03/22/2011 |
| 7913120 | Selective disabling of diagnostic functions within a data processing system A data processing system 2 has a memory 6 with a memory address space incorporating a plurality of domains, each domain comprising a set of memory addresses as defined by programmable domain specifying data 32. A processor core 8 executes... | 03/22/2011 |
| 7900020 | Correction of incorrect cache accesses The application describes a data processor operable to process data, and comprising: a cache in which a storage location of a data item within said cache is identified by an address, said cache comprising a plurality of storage locations and said data processor comp... | 03/01/2011 |
| 7900019 | Data access target predictions in a data processing system A data processing apparatus having a plurality of memories is provided in which address generation logic (109) outputs to at least one of the plurality of memories a target memory address corresponding to the data to be accessed. Target memory prediction logi... | 03/01/2011 |
| 7898278 | Power control circuitry, circuitry for analysing a switched power rail, and method of controlling connection of a power source to a switched power rail Power control circuitry is provided for controlling connection of a power source having a source voltage level to a switched power rail to provide power to an associated circuit block. The power control circuitry comprises a switch block for selectively connecting t... | 03/01/2011 |
| 7895469 | Integrated circuit using speculative execution An integrated circuit 2 is provided with a plurality of pipeline stages 10. These pipeline stages 10 have speculative processing control circuitry 12 which permits speculative processing in downstream pipeline stages and triggers a first ... | 02/22/2011 |
| 7895417 | Select-and-insert instruction within data processing systems A data processing system 2 is provided including an instruction decoder 34 responsive to program instructions within an instruction register 32 to generate control signals for controlling data processing circuitry 36. The instructions sup... | 02/22/2011 |
| 7893722 | Clock control of state storage circuitry State storage circuitry is described comprising a master-slave latch having tristate inverter circuitry 2 at its functional input and tristate scan signal insertion circuitry 12 for inserting scan data. The tristate scan signal insertion circuitry 1... | 02/22/2011 |
