Did You Know...
...that the Slinky toy was the result of a failed attempt by engineer Richard James to produce an antivibration device for ship instruments? His goal was to develop a spring that would instantaneously counterbalance the wave motion that rocks a ship at sea. Instead, he developed the Slinky.
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| Number | Title | Issue Date |
| 7710425 | Graphic memory management with invisible hardware-managed page faulting A computer system in which a graphics accelerator unit manages page faulting of texture data invisibly to the host processor. ... | 05/04/2010 |
| 7616200 | System for reducing aliasing on a display device An apparatus and method of displaying a first image on a display device with a plurality of pixels assigns one of a plurality of sample patterns to each pixel on the display device. Each pixel is assigned the one of a plurality of patterns based upon its unique loca... | 11/10/2009 |
| 7587520 | Image display system with visual server An image display system with one or more client computers in selective communication with a visual server having image processing capabilities. The client computer generates image modifying data corresponding to a generated image, and transmits the data to the visua... | 09/08/2009 |
| 7505036 | Order-independent 3D graphics binning architecture A binning architecture that allows opaque and transparent primitives to be segregated automatically into pairs of bins covering the same bin rectangle on the screen. When the frame is complete, the opaque bin will be rendered first and then the transparent bin will ... | 03/17/2009 |
| 7385608 | State tracking methodology Redundant changes of tracked state issued by an application are filtered out by comparing the new state value with the old value, and if they are the same, no update is made. State changes are collected in on-chip memory and added to the bin if the state vector asso... | 06/10/2008 |
| 7368831 | Power converter feedback circuit An apparatus for sensing and controlling remote load voltages, the apparatus includes a power converter, a plurality of remote loads, each remote load located in a loop connected to the power converter, and a feed back loop connected to the power converter, and phys... | 05/06/2008 |
| 7215344 | Triangle clipping for 3D graphics A geometry and lighting graphics accelerator with an improved clipping process. Clipping is performed prior to any calculation or evaluation of primitives for lighting, texture, fog, or color. Barycentric coordinates are used to define all vertices: original, interm... | 05/08/2007 |
| 6948087 | Wide instruction word graphics processor A graphics accelerator includes a vertex input for receiving vertex data, an output for forwarding processed data, and a processor coupled with the vertex input and output. The graphics accelerator also includes an instruction input that receives instructions for pr... | 09/20/2005 |
| 6894700 | Multisampling dithering with shuffle tables A system and method for generating random coverage masks for rendering images with transparent objects. The system uses shuffle tables for addresses of a pixel to index into a transparency table and to obtain a transparency mask, which is then ANDed with a coverage ... | 05/17/2005 |
| 6819332 | Antialias mask generation An antialiased mask generation technique where a patch of pixels is tested in parallel for fragment membership, and this test is looped with successive subpixel vector offsets from a programmed set. Antialiasing smoothness can be traded off for throughput by varying... | 11/16/2004 |
| 6816561 | Phase correction for multiple processors An apparatus for processing data includes a first processor and a second processor. The first processor receives a source clock signal and converts the source clock signal to a first timing signal with a first phase. The second processor receives the source clock si... | 11/09/2004 |
| 6766410 | System and method for reordering fragment data based upon rasterization direction A system and method for reordering data fragments to facilitate reads from a DDR SDRAM where the fragments are placed into a first and second data fragment buffer such that the data fragments are in sequential addresses whereby the second data read on the trailing e... | 07/20/2004 |
| 6765588 | Multisample dithering with shuffle tables A system and method for generating random coverage masks for rendering images with transparent objects. The system uses shuffle tables for addresses of a pixel to index into a transparency table and to obtain a transparency mask, which is then ANDed with a coverage ... | 07/20/2004 |
| 6734860 | Apparatus for providing videodriving capability from various types of DACS An apparatus for processing a graphical data stream for display on a display device includes a processor, a first conversion module and a second conversion module. The processor determines the characteristics of the graphical data stream. The first conversion module... | 05/11/2004 |
| 6700576 | Variable stride circle rendering apparatus and method An apparatus and method for rendering a circle with a radius on a display device comprises (a) providing a set of vertex points; (b) selecting a subset of vertex points from the set of vertex points based on the radius of the circle; (c) scaling each vert... | 03/02/2004 |
| 6690369 | Hardware-accelerated photoreal rendering A multiple-pass system for determining the primitives that are visible in a predetermined pick aperture for a "visible pick" operation. On the first pass, the primitives contained within the pick aperture and thus potentially visible are selected, and eac... | 02/10/2004 |
| 6683615 | Doubly-virtualized texture memory A graphics system in which the dedicated graphics memory is doubly virtualized: it can be paged into host physical memory, and also, beyond that, into host bulk storage. Portions of host physical memory which are needed to support the graphics memory mana... | 01/27/2004 |
| 6677954 | Graphics request buffer caching method A method for caching graphics-related data in one or more graphics request buffers wherein duplicative graphics-related data is not written to the graphics request buffers. In the preferred method the graphics-related data is sent in frames, and each fram... | 01/13/2004 |
| 6667930 | System and method for optimizing performance in a four-bank SDRAM An enhanced checkerboard pattern for optimizing performance when accessing a four-bank SDRAM. The screen is mapped using the enhanced checkerboard pattern, and each enhanced checkerboard pattern is composed of 16 squares. The enhanced checkerboard is made... | 12/23/2003 |
| 6667744 | High speed video frame buffer A device for storing pixel information for displaying a graphics image on a display includes a frame buffer and a processor. The information includes an intensity value and a value associated with each of a plurality of additional planes for each pixel. T... | 12/23/2003 |
| 6642928 | Multi-processor graphics accelerator An apparatus for displaying a polygon on a horizontal scan display device having a plurality of pixels includes first and second rasterizers that each process respective first and second sets of pixels. Each set of pixels includes vertical stripes that ar... | 11/04/2003 |
| 6628288 | Selectable back end unit A back end unit for use with a graphics processor includes an input for receiving graphics data streams from the graphics processor, an output for transmitting graphics data streams, and a plurality of paths, coupled with the input and output, that direct... | 09/30/2003 |
| 6597628 | Auto-disable receive control for DDR receive strobes A system for ensuring that erroneous data is not improperly latched in a gate when reading data from a DDR-SDRAM. The system is preferably a circuit that employs the last falling edge of a receive strobe to stop further variation of the receive strobe fro... | 07/22/2003 |
| 6597157 | Parallel phased switch control An integrated circuit controller for power conversion systems that provides for the control of parallel phased semiconductor switches without the need for separate filter inductors for each switch. The controller derivates two phased clock signals from a ... | 07/22/2003 |
| 6577316 | Wide instruction word graphics processor A graphics accelerator includes a vertex input for receiving vertex data, an output for forwarding processed data, and a processor coupled with the vertex input and output. The graphics accelerator also includes an instruction input that receives instruct... | 06/10/2003 |
| 6535216 | Multi-processor graphics accelerator An apparatus for displaying a polygon on a horizontal scan display device having a plurality of pixels includes first and second rasterizers that each process respective first and second sets of pixels. Each set of pixels includes vertical stripes that ar... | 03/18/2003 |
| 6529196 | Efficient stroking of vectors with arbitrary endpoints An improved device, of the type utilizing a display having pixels identified by a two-axis coordinate system, displays line segments referenced to the same coordinate system under control of a digital computer. The coordinate system, for example, having s... | 03/04/2003 |
| 6518971 | Graphics processing system with multiple strip breakers A graphics accelerator having first and second processors includes a first vertex breaker unit coupled to the first processor, and a second vertex breaker unit coupled to the second processor. The first breaker unit divides an incoming polygon strip into ... | 02/11/2003 |
| 6480913 | Data sequencer with MUX select input for converting input data stream and to specific output data stream using two exclusive-or logic gates and counter A system converts an input data stream in a first format (identified by a first stream code having at least two bits) into an output data stream in a second format. The system includes, among other things, a data sequencer for sequencing the input data st... | 11/12/2002 |
| 6476816 | Multi-processor graphics accelerator An apparatus for displaying a polygon on a horizontal scan display device having a plurality of pixels includes first and second rasterizers that each process respective first and second sets of pixels. Each set of pixels includes vertical stripes that ar... | 11/05/2002 |
| 6459453 | System for displaying a television signal on a computer monitor An apparatus and method for displaying a television signal on a computer monitor first receives a selected first field data block of the television signal for display by the monitor. The television signal preferably includes a stream of first field data b... | 10/01/2002 |
| 6313845 | Method and apparatus for transporting information to a graphic accelerator card A graphics request stream is transferred from a host processor to a graphics card via a host bus so that the stream traverses the host bus no more than once. To that end, the graphics card has a graphics card memory, and the host processor has a host memo... | 11/06/2001 |
| 6253261 | System and method for direct memory access in a computer system A system and method for improving the efficiency of DMA transfers. In particular, a "continue" command is provided for DMA block transfers. In practice, this command allows the system to begin a DMA transfer before the entire size of the transfer block is... | 06/26/2001 |
| 6188410 | System for processing vertices from a graphics request stream An apparatus for processing a graphics request stream begins processing subsequent vertex data while processing previous vertex data. To that end, the apparatus has a vertex assembler having an input for receiving graphics requests, and a processor (coupl... | 02/13/2001 |
| 6184666 | Buck converter with parallel switches A converter for reducing the amplitude of a DC input signal includes first and second switches that each are coupled between an input port for receiving the input signal, and voltage reducing circuitry for reducing the amplitude of the input signal. The t... | 02/06/2001 |
| 6181355 | Graphics processing with transcendental function generator A graphics processor for processing vertices of a polygon includes an input for receiving an instruction for processing a given vertex, memory for storing a first lookup table and a second lookup table, and an interpolation engine that, responsive to rece... | 01/30/2001 |
| 6025853 | Integrated graphics subsystem with message-passing architecture A graphics processing chip which uses a deep pipeline of multiple asynchronous units to achieve a high net throughput in 3D rendering. Preferably reads and writes to a local buffer are provided by separate stages of the pipeline. Preferably some of the in... | 02/15/2000 |
| 5815166 | Graphics subsystem with slaveable rasterizer A graphics processing system with a message-passing architecture, in which the rasterizer can be bypassed by a particular type of message from the host. This permits rasterization to be slaved to the host downloads and bitmasks, so that images and pattern... | 09/29/1998 |
| 5805868 | Graphics subsystem with fast clear capability A graphics subsystem in which a very fast clear operation is performed without the need to address each pixel, and without using memories which include a hardware fast-clear capability. This is implemented by using a reference frame counter: the window is... | 09/08/1998 |
| 5798770 | Graphics rendering system with reconfigurable pipeline sequence The preferred embodiment discloses a pipelined graphics processor in which the sequence can be dynamically reconfigured (e.g. between primitives) in a rendering sequence. The pipeline sequence can be configured for compliance with specifications such as O... | 08/25/1998 |
