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A method of swing on a swing is disclosed, in which a user positioned on a standard swing suspended by two chains from a substantially horizontal tree branch induces side to side motion by pulling alternately on one chain and then the other.
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| Application No. | Application Title | Issue Date |
| 20120131417 | CLASSIFYING A CRITICALITY OF A SOFT ERROR AND MITIGATING THE SOFT ERROR BASED ON THE CRITICALITY Methods and systems mitigate a soft error in an integrated circuit. A map is stored in a memory, and the map specifies a criticality class for each storage bit in the integrated circuit. A mitigative technique is associated with each criticality class. The soft error is... | 05/24/2012 |
| 20120032326 | AIR THROUGH-SILICON VIA STRUCTURE A silicon substrate has a conductive via extending from a first surface of the silicon substrate through the silicon substrate to a second surface of the silicon substrate. A dielectric via extends from the second surface of the silicon substrate toward the first surfac... | 02/09/2012 |
| 20120019292 | CONFIGURATION OF A MULTI-DIE INTEGRATED CIRCUIT An embodiment of an integrated circuit (IC) is described. This embodiment of the IC includes an interposer; a first die on an interposer, where the first die generates a global signal propagated through the interposer; and a second die on the surface of the interposer a... | 01/26/2012 |
| 20110276321 | DEVICE SPECIFIC CONFIGURATION OF OPERATING VOLTAGE A method and circuit for device specific configuration of an operating voltage is provided. A circuit design is analyzed to determine a maximum gate-level delay for the circuit design. A minimum voltage value corresponding to the maximum gate-level delay is determined a... | 11/10/2011 |
| 20120007188 | INTEGRATED CIRCUIT DEVICE WITH STRESS REDUCTION LAYER An integrated circuit device is disclosed that includes a dual stress liner NMOS device having a tensile stress layer that overlies a NMOS gate film stack, a dual stress liner PMOS device having a compressive stress layer that overlies a PMOS gate film stack, a reduced-... | 01/12/2012 |
| 20120002392 | ELECTRO-STATIC DISCHARGE PROTECTION FOR DIE OF A MULTI-CHIP MODULE Electro-static discharge (“ESD”) protection for a die of a multi-chip module is described. A contact has an externally exposed surface after formation of the die and prior to assembly of the multi-chip module. The contact is for a die-to-die interconnect of the mult... | 01/05/2012 |
| 20110316572 | TESTING DIE-TO-DIE BONDING AND REWORK A method of testing a multi-die integrated circuit (IC) can include testing an inter-die connection of the multi-die IC. The inter-die connection can include a micro-bump coupling a first die to a second die. The method can include detecting whether a fault occurs durin... | 12/29/2011 |
| 20110302356 | SCALABLE MEMORY INTERFACE SYSTEM A memory interface system can include a memory controller configured to operate at a first operating frequency. A physical interface block can be coupled to the memory controller. The physical interface block can be configured to communicate with the memory controller a... | 12/08/2011 |
| 20110299351 | INPUT/OUTPUT BANK ARCHITECTURE FOR AN INTEGRATED CIRCUIT An integrated circuit can include an input/output (I/O) bank. The I/O bank can include a plurality of byte clock groups. Each byte clock group can include at least one phaser configured to clock circuit elements of the byte clock group at a frequency at which a source s... | 12/08/2011 |
| 20110299347 | DYNAMIC DETECTION OF A STROBE SIGNAL WITHIN AN INTEGRATED CIRCUIT A method of processing a strobe signal can include oversampling a strobe signal received from a source synchronous device and determining an amount of time between sending a read request to the source synchronous device and detecting a first pulse of the strobe signal a... | 12/08/2011 |
| 20110298511 | STROBE SIGNAL MANAGEMENT TO CLOCK DATA INTO A SYSTEM A method of communicating with a source synchronous device can include determining an expected number of pulses of a strobe signal to be received in response to a first read request directed to the source synchronous device and receiving the strobe signal from the sourc... | 12/08/2011 |
| 20110291758 | DIFFERENTIAL COMPARATOR CIRCUIT HAVING A WIDE COMMON MODE INPUT RANGE In one embodiment of the invention, a circuit arrangement is provided. The circuit arrangement includes a plurality of differential amplifiers, coupled in parallel, including at least a first differential amplifier and a second differential amplifier. Each differential ... | 12/01/2011 |
| 20110291287 | THROUGH-SILICON VIAS WITH LOW PARASITIC CAPACITANCE A device has a silicon substrate with a via extending from a first surface of the silicon substrate having a conductor portion. A first dielectric portion surrounds the conductor portion. A second dielectric portion is disposed between a first silicon portion and the si... | 12/01/2011 |
| 20110254602 | LOCKSTEP SYNCHRONIZATION AND MAINTENANCE A method and circuit are provided for synchronizing a first circuit and a second circuit. The first and second circuits are signaled to each generate respective waveform outputs. A phase difference is determined between the generated waveform output from the first and s... | 10/20/2011 |
| 20110252244 | METHOD AND INTEGRATED CIRCUIT FOR SECURE ENCRYPTION AND DECRYPTION In one embodiment of the present invention, a secure cryptographic circuit arrangement is provided. The secure cryptographic circuit includes a cryptographic processing block, a spreading sequence generator, and a delay control circuit. The cryptographic processing bloc... | 10/13/2011 |
| 20110248811 | STACKED DUAL INDUCTOR STRUCTURE The dual inductor structure can include a first inductor including a first plurality of coils. Each coil of the first plurality of coils can be disposed within a different one of a plurality of conductive layers. The coils of the first plurality of coils can be vertical... | 10/13/2011 |
| 20110248787 | VARACTOR CIRCUIT AND VOLTAGE-CONTROLLED OSCILLATION A varactor circuit and voltage-controlled oscillation are described. The varactor circuit includes a first varactor, a second varactor, a third varactor, and a fourth varactor. A first source-drain node of the first varactor and a second source-drain node of the second ... | 10/13/2011 |
| 20110222590 | SYSTEM AND METHOD FOR PILOT TONE ASSISTED SELECTED MAPPING A method is provided for communicating a data value and pilot tone within the same communication sub-carrier of a communication channel. A first reference phase corresponding to a first data value is selected. A pilot tone having the first reference phase is generated. ... | 09/15/2011 |
| 20110215834 | PROGRAMMABLE INTEGRATED CIRCUIT WITH MIRRORED INTERCONNECT STRUCTURE A programmable integrated circuit (IC) with mirrored interconnect structure. The IC includes a plurality of arrangements, which are horizontally arranged. Each arrangement includes a first logic column, an interconnect column, and a second logic column. Each interconnec... | 09/08/2011 |
| 20110215465 | MULTI-CHIP INTEGRATED CIRCUIT An integrated circuit (IC) combines a first IC chip (die) having a first on-chip interconnect structure and a second IC chip having a second on-chip interconnect structure on a reconstructed wafer base. The second IC chip is edge-bonded to the first IC chip with oxide-t... | 09/08/2011 |
| 20110210443 | SEMICONDUCTOR DEVICE HAVING BUCKET-SHAPED UNDER-BUMP METALLIZATION AND METHOD OF FORMING SAME An embodiment of a method of forming a semiconductor device that includes a substrate having an active layer and interconnect formed on the active layer is described. The method includes: forming a dielectric layer above the interconnect having a tapered via exposing at... | 09/01/2011 |
| 20110191729 | Method and Apparatus for Interconnect Layout in an Integrated Circuit An embodiment of the invention relates to a computer-implemented method of designing an integrated circuit (IC). In this embodiment, layout data describing conductive layers of the integrated circuit on a substrate is generated according to design specification data for... | 08/04/2011 |
| 20110147949 | HYBRID INTEGRATED CIRCUIT DEVICE An embodiment of a method to form a hybrid integrated circuit device is described. This embodiment of the method comprises: forming a first die using a first lithography, where the first die is on a substrate; and forming a second die using a second lithography, where t... | 06/23/2011 |
| 20110125819 | MINIMUM MEAN SQUARE ERROR PROCESSING A first systolic array receives an input set of time division multiplexed matrices from a plurality of channel matrices. In a first mode, the first systolic array performs triangularization on the input matrices, producing a first set of matrices, and in a second mode p... | 05/26/2011 |
| 20110124333 | FEMTOCELL CONFIGURATION USING SPECTRUM SENSING An embodiment of the present invention provides for the ad-hoc configuration of femtocells using spectrum sensing for the selection of spectrum channels. One or more embodiments of the invention determine frequency bands that are not reserved by macrocells in a location... | 05/26/2011 |
| 20110121438 | EXTENDED UNDER-BUMP METAL LAYER FOR BLOCKING ALPHA PARTICLES IN A SEMICONDUCTOR DEVICE An integrated circuit (IC) has an under-bump metal (UBM) pad disposed between a solder bump and a semiconductor portion of the IC. The UBM pad has a contact perimeter formed with the solder bump. The UBM pad extends beyond the contact perimeter a sufficient distance to ... | 05/26/2011 |
| 20110113401 | T-COIL NETWORK DESIGN FOR IMPROVED BANDWIDTH AND ELECTROSTATIC DISCHARGE IMMUNITY A method of generating a circuit design comprising a T-coil network includes determining inductance for inductors and a parasitic bridge capacitance of the T-coil network. The parasitic bridge capacitance is compared with a load capacitance metric that depends upon para... | 05/12/2011 |
| 20110095851 | HIGH IMPEDANCE ELECTRICAL CONNECTION VIA Vias for differential signals are typically of a lower impedance than the signal lines connected to them. The noise and reflected signals resulting in impedance mismatch may require circuits to be operated at a frequency far lower than desired. One or more embodiments o... | 04/28/2011 |
| 20110058290 | SHARED ELECTROSTATIC DISCHARGE PROTECTION FOR INTEGRATED CIRCUIT OUTPUT DRIVERS A system for protecting metal oxide semiconductor field effect transistor (MOSFET) output drivers within an integrated circuit (IC) from an electrostatic discharge (ESD) includes a first MOSFET output driver and a second MOSFET output driver positioned within a common I... | 03/10/2011 |
| 20110026173 | ENHANCED IMMUNITY FROM ELECTROSTATIC DISCHARGE Enhanced electrostatic discharge (“ESD”) protection for an integrated circuit is described. An embodiment relates generally to a circuit for protection against ESD. The circuit has an input/output node and a driver. The driver has a first transistor and a second tra... | 02/03/2011 |
| 20110012633 | APPARATUS AND METHOD FOR TESTING OF STACKED DIE STRUCTURE An integrated circuit device is described that includes a stacked die and a base die having probe pads that directly couple to test logic of the base die so as to implement a scan chain for testing of the integrated circuit device. The base die further includes contacts... | 01/20/2011 |
| 20100322352 | SPHERE DETECTOR PERFORMING DEPTH-FIRST SEARCH UNTIL TERMINATED Systems and methods detect a communication received at receiving antennas from transmitting antennas. Each transmitting antenna transmits a symbol in a constellation. A sphere detector performs a depth-first search until the depth-first search terminates in response to ... | 12/23/2010 |
| 20100308910 | APPARATUS AND METHOD FOR PREDICTIVE OVER-DRIVE DETECTION A method and apparatus for efficient drive level selection for, e.g., power amplifiers utilized within a wireless communication system, which utilizes digital predistortion (DPD) to adaptively and predictively select drive level. The DPD, e.g., increases the power ampli... | 12/09/2010 |
| 20100272195 | PEAK-TO-AVERAGE POWER RATIO REDUCTION WITH BOUNDED ERROR VECTOR MAGNITUDE Method and apparatus for signal processing to minimize the peak to average power ratio of an Orthogonal Frequency Division Multiplexing (“OFDM”) or Orthogonal Frequency Division Multiple Access (“OFDMA”) signal with bounded error vector magnitude for an integrat... | 10/28/2010 |
| 20100258877 | INTEGRATED CIRCUIT DEVICE WITH STRESS REDUCTION LAYER An integrated circuit device is disclosed that includes a dual stress liner NMOS device having a tensile stress layer that overlies a NMOS gate film stack, a dual stress liner PMOS device having a compressive stress layer that overlies a PMOS gate film stack, a reduced-... | 10/14/2010 |
| 20100201883 | INTEGRATED CIRCUIT HAVING A CIRCUIT FOR AND METHOD OF PROVIDING INTENSITY CORRECTION FOR A VIDEO A method of providing intensity correction for a video is disclosed. The method may comprise evaluating a portion of a frame of the video; determining a difference in intensity of a current block of the frame with the corresponding block of the previous frame; correctin... | 08/12/2010 |
| 20100199136 | METHOD AND APPARATUS FOR DETECTING AND CORRECTING ERRORS IN A PARALLEL TO SERIAL CIRCUIT A circuit has first portion that receives data at a first rate; a second portion that outputs data at a second rate synchronized to and different from the first rate; a third portion that transfers data from the first portion to the second portion; and a fourth portion ... | 08/05/2010 |
| 20100193870 | TECHNIQUES FOR IMPROVING TRANSISTOR-TO-TRANSISTOR STRESS UNIFORMITY An integrated circuit (100) has a transistor with an active gate structure 108 overlying an active diffusion area 112 formed in a semiconductor substrate 126. A dummy gate structure 110 is formed over a diffusion area and separated fro... | 08/05/2010 |
| 20100193229 | BARRIER LAYER TO PREVENT CONDUCTIVE ANODIC FILAMENTS A through hole is formed in a circuit board (300) that has fibers (312) dispersed in a polymer matrix. Copper is sputtered within the through hole to form a sufficiently conductive layer for electrolytic plating (308) over the sputtered copper layer... | 08/05/2010 |
| 20100192118 | METHOD OF AND CIRCUIT FOR IMPLEMENTING A FILTER IN AN INTEGRATED CIRCUIT According to an embodiment of the invention, a method of configuring a filter in a circuit to be implemented in an integrated circuit is disclosed. The method comprises receiving a high level design of the circuit; identifying a filter in the high level design; analyzin... | 07/29/2010 |
