Bizarre Patents
Mouthguard made at least partially from an edible candy
A mouthguard includes a U-shaped upper bite plate which removably fits over upper teeth of a person, with the entire upper bite plate being made from a soft, deformable and edible gummi candy.
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| Application No. | Application Title | Issue Date |
| 20120131401 | SYSTEM AND METHOD FOR SHARING A COMMUNICATIONS LINK BETWEEN MULTIPLE COMMUNICATIONS PROTOCOLS A system and method for sharing a communications link between multiple protocols is described. A system includes a communications interface configured to exchange information with other systems using at least one of a plurality of protocols; a protocol select register t... | 05/24/2012 |
| 20120131309 | HIGH-PERFORMANCE, SCALABLE MUTLICORE HARDWARE AND SOFTWARE SYSTEM Traditionally, providing parallel processing within a multi-core system has been very difficult. Here, however, a system in provided where serial source code is automatically converted into parallel source code, and a processing cluster is reconfigured “on the fly” ... | 05/24/2012 |
| 20120129456 | Systems and Methods for Silencing Wireless Devices Embodiments provide systems and methods to optimize the time when to receive transmissions from dissimilar wireless networks, and hence, improve the overall network throughput and avoid access point transmission rate fall-back mechanism having an avalanche effect during... | 05/24/2012 |
| 20120128236 | METHOD AND APPARATUS FOR STEREO MISALIGNMENT ESTIMATION USING MODIFIED AFFINE OR PERSPECTIVE MODEL A method and apparatus for estimating stereo misalignment using modified affine or perspective model. The method includes dividing a left frame and a right frame into blocks, comparing horizontal and vertical boundary signals in the left frame and the right frame, estim... | 05/24/2012 |
| 20120128168 | METHOD AND APPARATUS FOR NOISE AND ECHO CANCELLATION FOR TWO MICROPHONE SYSTEM SUBJECT TO CROSS-TALK A method and apparatus for joint noise and echo cancellation of a two microphone system subject to cross-talk. The method includes estimating the reference output by removing the cross-talk and the estimated echo from the reference channel, when an echo is detected in t... | 05/24/2012 |
| 20120127783 | SRAM Cell for Single Sided Write A first integrated circuit containing a single sided write SRAM cell array, each SRAM cell having a bit passgate and an auxiliary bit-bar driver transistor. A process of operating the first integrated circuit including a single sided read operation in which source nodes... | 05/24/2012 |
| 20120127777 | METHOD TO IMPROVE FERROELECTRIC MEMORY PERFORMANCE AND RELIABILITY One embodiment of the present invention relates to a method by which the imprint of a ferroelectric random access memory (FRAM) array is reduced. The method begins when an event that will cause imprint to the memory array is anticipated by an external agent to the devic... | 05/24/2012 |
| 20120126781 | ON-CHIP IR DROP DETECTORS FOR FUNCTIONAL AND TEST MODE SCENARIOS, CIRCUITS, PROCESSES AND SYSTEMS An integrated circuit includes a functional circuit (10) having a power grid (20) with a set of power grid points (30.i) for monitoring; and an electronic monitoring circuit (100) that has a variably operable reference circuit (150<... | 05/24/2012 |
| 20120126624 | HIGH EFFICIENCY WIDE LOAD RANGE BUCK/BOOST/BRIDGE PHOTOVOLTAIC MICRO-CONVERTER Series strings of photovoltaic (PV) modules with integrated dc-dc microconverters that can function in buck, boost, or an intermediate bridge mode based on the load can harvest more energy than conventional central-inverter architectures, especially when the arrays are ... | 05/24/2012 |
| 20120126453 | PELLET LOADER WITH PELLET SEPARATOR FOR MOLDING IC DEVICES A pellet loading apparatus includes a tablet pusher including a support surfaces including a pusher mechanism coupled thereto for vertical movement upon actuation. A tablet holder on the tablet pusher includes locations framed by sidewall members aligned in the vertical... | 05/24/2012 |
| 20120126418 | INTEGRATED CIRCUIT DEVICE HAVING DIE BONDED TO THE POLYMER SIDE OF A POLYMER SUBSTRATE An integrated circuit (IC) device includes a polymer substrate having a topside surface and a bottomside surface opposite the topside surface, a plurality of through-holes that extend from the topside surface to the bottomside surface, and a plurality of bottom metal pa... | 05/24/2012 |
| 20120126385 | METHOD FOR SEMICONDUCTOR LEADFRAMES IN LOW VOLUME AND RAPID TURNAROUND A leadframe for a QFN/SON semiconductor device comprising a strip of a first metal as the leadframe core with a plurality of leads and a pad. a layer of a second metal over both surfaces of the strip. There are sidewalls normal to the surfaces. The first metal exposed a... | 05/24/2012 |
| 20120126383 | METHOD FOR SEMICONDUCTOR LEADFRAMES IN LOW VOLUME AND RAPID TURNAROUND An apparatus comprising a metallic leadframe including a pad and a plurality of leads. Each having a first and a parallel second surface and sidewalls normal to the surfaces. The pad and each lead having a core of a first metal and layers of a second metal different fro... | 05/24/2012 |
| 20120126298 | SELF-POWERED INTEGRATED CIRCUIT WITH PHOTOVOLTAIC CELL A photovoltaic cell is provided as a composite unit together with elements of an integrated circuit on a common substrate. In a described embodiment, connections are established between a photovoltaic cell portion and a circuitry portion of an integrated structure to en... | 05/24/2012 |
| 20120126247 | SELF-POWERED INTEGRATED CIRCUIT WITH MULTI-JUNCTION PHOTOVOLTAIC CELL A photovoltaic cell is provided as a composite unit together with elements of an integrated circuit on a common substrate. In a described embodiment, connections are established between a multiple photovoltaic cell portion and a circuitry portion of an integrated struct... | 05/24/2012 |
| 20120110659 | LESS-SECURE PROCESSORS, INTEGRATED CIRCUITS, WIRELESS COMMUNICATIONS APPARATUS, METHODS AND PROCESSES OF MAKING An integrated circuit (122) includes an on-chip boot ROM (132) holding boot code, a non-volatile security identification element (140) having non-volatile information determining a less secure type or more secure type, and a processor (130). ... | 05/03/2012 |
| 20120110351 | POWER MANAGEMENT FOR DIGITAL DEVICES In a digital device, activity of (or load on) one or more processors, peripherals and memory buses are measured. A power management framework operated in the digital device bases power settings in the digital device on the measured loads, and accordingly issues power ma... | 05/03/2012 |
| 20120108076 | SHOWERHEAD FOR CVD DEPOSITIONS A CVD showerhead that includes a circular inner showerhead and at least one outer ring showerhead. At least two process gas delivery tubes are coupled to each showerhead. Also, a dual showerhead that includes a circular inner showerhead and at least one outer ring showe... | 05/03/2012 |
| 20120108068 | Method for Patterning Sublithographic Features A method of uniformly shrinking hole and space geometries by forming sidewalls of an ALD film deposited at low temperature on a photolithographic pattern.... | 05/03/2012 |
| 20120108066 | PECVD SHOWERHEAD CONFIGURATION FOR CMP UNIFORMITY AND IMPROVED STRESS A dielectric deposition tool for forming a silicon dioxide layer on a wafer with a TEOS showerhead which delivers a flow rate per unit area from an edge band of the showerhead that is at least twice a flow rate per unit area from a central region of the showerhead. The ... | 05/03/2012 |
| 20120108027 | IMPROVED SILICIDE METHOD A process for forming an integrated circuit with reduced sidewall spacers to enable improved silicide formation between minimum spaced transistor gates. A process for forming an integrated circuit with reduced sidewall spacers by first forming sidewall spacer by etching... | 05/03/2012 |
| 20120108021 | PMOS SiGe-LAST INTEGRATION PROCESS A process of forming a CMOS integrated circuit including integrating SiGe source/drains in the PMOS transistor after source/drain and LDD implants and anneals. A dual layer hard mask is formed on a polysilicon gate layer. The bottom layer prevents SiGe growth on the pol... | 05/03/2012 |
| 20120108020 | LOW TEMPERATURE COEFFICIENT RESISTOR IN CMOS FLOW A method for adding a low TCR resistor to a baseline CMOS manufacturing flow. A method of forming a low TCR resistor in a CMOS manufacturing flow. A method of forming an n-type and a p-type transistor with a low TCR resistor in a CMOS manufacturing flow.... | 05/03/2012 |
| 20120107729 | GATE CD CONTROL USING LOCAL DESIGN ON BOTH SIDES OF NEIGHBORING DUMMY GATE LEVEL FEATURES A method of forming an IC including MOS transistors includes using a gate mask to form a first active gate feature having a line width W1 over an active area and a neighboring dummy feature having a line width 0.8W1 to 1.3W1. The neighbo... | 05/03/2012 |
| 20120107552 | Chip Attachment Layer Having Traverse-Aligned Conductive Filler Particles A method for conductively attaching a workpiece (110) onto a substrate (101). Spreading a layer of an adhesive polymeric compound (130) over the first surface (101a) of the substrate, the compound including a suspension of electrically... | 05/03/2012 |
| 20120106614 | SYSTEM AND METHOD FOR CHANNEL INTERPOLATION A system and method for channel interpolation in a wireless device. In one embodiment a wireless device includes a channel estimator. The channel estimator is configured to generate estimated channel coefficients for a wireless channel over which the wireless device rec... | 05/03/2012 |
| 20120106611 | PHASE LOCKING LOOP A phase-locking loop (PLL) for use with orthogonal frequency division multiplexed signals. In one embodiment, a wireless receiver includes a PLL is configured to reduce phase and frequency divergence between the wireless receiver and a transmitter of a packet received b... | 05/03/2012 |
| 20120106609 | SYSTEM AND METHOD FOR CHANNEL CLASSIFICATION A system and method for classifying a channel with regard to delay spread in a wireless network applying orthogonal frequency division multiplexing. In one embodiment, a wireless receiver includes a channel classifier. The channel classifier is configured to compute a c... | 05/03/2012 |
| 20120106602 | Signaling in a Medical Implant Based System Signaling in a medical implant based system. A method includes transmitting bits modulated with a predefined sequence in a band of channels by a first medical transceiver. The method includes transmitting bits modulated with a first predefined sequence of a plurality of... | 05/03/2012 |
| 20120106528 | UNIFIED PROTOCOL STACK FOR COLOCATED WIRELESS TRANSCEIVERS A system and method for accessing a wireless network via unified protocol stack. In one embodiment a wireless networking system includes a wireless device. The wireless device includes a first wireless transceiver, a second wireless transceiver, a processor, and a unifi... | 05/03/2012 |
| 20120106418 | CLIENT' DEVICE POWER REDUCTION IN WIRELESS NETWORKS HAVING NETWORK-COMPUTED CLIENT' LOCATION A method of reducing client power consumption in a wireless network including a network server which provides computed client' locations, at least one access point (AP), and a plurality of wireless stations (STAs) including a first wireless station (STA1). The AP period... | 05/03/2012 |
| 20120106381 | SYSTEM AND METHOD FOR SOFT ACCESS POINT POWER REDUCTION A system and method for reducing power consumption of a wireless device operating as a soft access point. In one embodiment, a wireless device includes a soft access point controller that configures the wireless device to operate as a group owner in a peer-to-peer wirel... | 05/03/2012 |
| 20120106225 | Array-Based Integrated Circuit with Reduced Proximity Effects An integrated circuit and method of generating a layout for an integrated circuit in which circuitry peripheral to an array of repetitive features, such as memory or logic cells, is realized according to devices constructed similarly as the cells themselves, in one or m... | 05/03/2012 |
| 20120106211 | POWER FACTOR AND LINE DISTORTION METHOD AND APPARATUS Today, power distribution systems can be used to supply power to many loads, and since many loads, such as servers, are reactive (i.e., have capacitors and/or inductors), line distortion and power factor can be an issue. Conventional techniques to correct for line disto... | 05/03/2012 |
| 20120105992 | METHOD AND CIRCUITRY FOR PROGRAMMABLY CONTROLLING DEGAUSS WRITE CURRENT DECAY IN HARD DISK DRIVES A control circuit to provide a control current to control an amplitude of a write current in a magnetic media drive. The control circuit has an output circuit for providing the control current with an amplitude dependent on a bias voltage. A bias current path provides t... | 05/03/2012 |
| 20120105261 | ADC CHANNEL SELECTION AND CONVERSION A microcontroller includes a microcontroller core and an analog-to-digital converter (“ADC”) coupled to said microcontroller core. The ADC has multiple input channel multiplexers that are configured to receive multiple analog input channels. The microcontroller furt... | 05/03/2012 |
| 20120105046 | CURRENT MIRROR USING AMBIPOLAR DEVICES Current mirrors have been used in analog electronics with both CMOS and bipolar transistors for many years. Conventional current minor designs, though, may not be suitable for emerging technology transistors, such as graphene transistors, carbon nanotube (CNT) transisto... | 05/03/2012 |
| 20120105009 | SYSTEMS AND METHODS FOR DETERMINING BATTERY STATE OF CHARGE Systems (50, 200) and methods for determining a state of charge of a battery (52, 102, 150, 202) are provided. The system (50, 200) includes a power source (56, 206) configured to provide a charging current to a battery (52, 102, 150, 202<... | 05/03/2012 |
| 20120104604 | CRACK ARREST VIAS FOR IC DEVICES An integrated circuit (IC) device includes a substrate having a top surface including active circuitry including a plurality of I/O nodes, and a plurality of die pads coupled to the plurality of I/O nodes. A first dielectric layer including first dielectric vias is over... | 05/03/2012 |
| 20120104540 | TRENCH WITH REDUCED SILICON LOSS An isolation trench in a substrate of a semiconductor device includes a first shallow portion, a transition region, and a second deeper portion. The isolation trench contains a dielectric filler. The isolation trench is formed by first forming a first shallow portion of... | 05/03/2012 |
