Assignee: Silicon Storage Technology, Inc.

Location: Sunnyvale, CA, US
No. of applications: 38

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Browse applications

Application No.	Application Title	Issue Date
20120044774	SENSE AMPLIFIER FOR LOW VOLTAGE HIGH SPEED SENSING A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of th...	02/23/2012
20110169558	CHARGE PUMP SYSTEMS AND METHODS Digital multilevel memory systems and methods include a charge pump for generating regulated high voltages for various memory operations. The charge pump may include a plurality of pump stages. Aspects of exemplary systems may include charge pumps that performs orderly ...	07/14/2011
20110121863	SENSE AMPLIFIER FOR LOW VOLTAGE HIGH SPEED SENSING A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of th...	05/26/2011
20110121799	Fast Voltage Regulators For Charge Pumps A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start u...	05/26/2011
20110058425	Integrated Flash Memory Systems And Methods For Load Compensation Systems and methods are disclosed including features that compensate for variations in the magnitude of supply voltages used in memory arrays. According to some aspects, compensation circuits may provide a tunable current-limiting load for data columns, where the load c...	03/10/2011
20110022905	Test Circuit and Method for Multilevel Cell Flash Memory A test device and method may be used to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system....	01/27/2011
20110018634	Method and Apparatus for Systematic and Random Variation and Mismatch Compensation for Multilevel Flash Memory Operation Method and means for random or systematic mismatch compensation for a memory sensing system are disclosed. A sense amplifier includes a bulk voltage source to set the bulk of the sensing transistor to be a voltage different than the voltage driving the sensing transisto...	01/27/2011
20110018624	INTEGRATED POWER DETECTOR WITH TEMPERATURE COMPENSATION FOR FULLY-CLOSED LOOP CONTROL An amplifier circuit comprises a detection power input circuit for receiving an RF signal, and a bias circuit that includes an output for generating a bias signal in response to a reference control voltage. The power detector further comprises a detection circuit for ge...	01/27/2011
20100322015	Split Gate NAND Flash Memory Structure and Array, Method of Programming, Erasing and Reading Thereof, and Method of Manufacturing A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type in the substrate with a second region of the second conductivity type in the substrate...	12/23/2010
20100254207	Non-Volatile Memory Device with Plural Reference Cells, and Method of Setting the Reference Cells A non-volatile memory device has an array of non-volatile memory cells, a first plurality of non-volatile memory reference cells, with each reference cell capable of being programmed to a reference level different from the other reference cells; and a second plurality o...	10/07/2010
20100203654	Method of Testing an Integrated Circuit Die, and an Integrated Circuit Die In the present invention, a method of testing an unpackaged integrated circuit die is disclosed. The die has a plurality of first input/output pads. A serial electrical connection is fabricated in the die between all of the input/output pads of the die which are not of ...	08/12/2010
20100202200	Power Line Compensation for Flash Memory Sense Amplifiers In one aspect, the invention concerns a memory system that compensates for power level variations in sense amplifiers for multilevel memory. For example, a compensation circuit can be employed to compensate for current or voltage variations in the power supplied to mult...	08/12/2010
20100188138	Fast Start Charge Pump for Voltage Regulators A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start u...	07/29/2010
20100157687	Method for Erasing a Flash Memory Cell or an Array of Such Cells Having Improved Erase Coupling Ratio A flash memory cell is of the type having a substrate of a first conductivity type having a first region of a second conductivity type at a first end, and a second region of the second conductivity type at a second end, spaced apart from the first end, with a channel re...	06/24/2010
20100091567	Test Circuit and Method for Multilevel Cell Flash Memory A test device and method may be used to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system....	04/15/2010
20100067311	Non-Volatile Memory Device Having High Speed Serial Interface A non-volatile memory device comprises an interface circuit for receiving a plurality of signals. The plurality of signals provides multiplexed address and data and command signals in a serial format. An input buffer stores a plurality of the plurality of signals receiv...	03/18/2010
20100067308	Sub Volt Flash Memory System Various circuits include MOS transistors that have a bulk voltage terminal for receiving a bulk voltage that is different from a supply voltage and ground. The bulk voltage may be selectively set so that some MOS transistors have a bulk voltage set to the supply voltage...	03/18/2010
20100054043	Split Gate Non-Volatile Flash Memory Cell Having a Floating Gate, Control Gate, Select Gate and an Erase Gate with an Overhang Over the Floating Gate, Array and Method of Manufacturing An improved split gate non-volatile memory cell is made in a substantially single crystalline substrate of a first conductivity type, having a first region of a second conductivity type, a second region of the second conductivity type, with a channel region between the ...	03/04/2010
20100001765	SENSE AMPLIFIER FOR LOW VOLTAGE HIGH SPEED SENSING A memory system includes a sense amplifier for detecting content of data memory cells by comparison with a voltage stored in a reference cell. The sense amplifier may comprise a comparator, first and second load circuits, and a low impedance circuit. A first input of th...	01/07/2010
20090323415	FLASH MEMORY ARRAY SYSTEM INCLUDING A TOP GATE MEMORY CELL A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. Th...	12/31/2009
20090303803	Independent Bi-Directional Margin Control Per Level and Independently Expandable Reference Cell Levels for Voltage Mode Sensing A memory system includes reference level generators that may provide programmable margins, and programmable verify voltage levels. The reference levels may be shifted within a range of voltages with varying differences between reference voltage levels and with different...	12/10/2009
20090302830	INTEGRATED POWER DETECTOR WITH TEMPERATURE COMPENSATION FOR FULLY-CLOSED LOOP CONTROL An amplifier circuit comprises a detection power input circuit for receiving an RF signal, and a bias circuit that includes an output for generating a bias signal in response to a reference control voltage. The power detector further comprises a detection circuit for ge...	12/10/2009
20090160411	FAST VOLTAGE REGULATORS FOR CHARGE PUMPS A digital multilevel memory system includes a charge pump and a voltage regulator for generating regulated high voltages for various memory operations. The charge pump may include a plurality of boost circuits to boost the output of the charge pump during a fast start u...	06/25/2009
20090150588	Hard Disk Drive Cache Memory and Playback Device A NOR emulating device using a controller and NAND memories can be used in a computer system in placed of the main memory or in place of the BIOS NOR memory. Thus, the emulating device can function as a bootable memory. In addition, the device can act as a cache to the ...	06/11/2009
20090147579	NON-VOLATILE MEMORY SYSTEMS AND METHODS INCLUDING PAGE READ AND/OR CONFIGURATION FEATURES A high speed voltage mode sensing is provided for a digital multibit non-volatile memory integrated system. An embodiment has a local source follower stage followed by a high speed common source stage. Another embodiment has a local source follower stage followed by a h...	06/11/2009
20090140814	RF POWER AMPLIFIER An RF power amplifier includes a plurality of amplifier cells. Each amplifier cell includes a bipolar transistor and a base circuit that comprises an RF coupling capacitor, a bias resistor, a base capacitor, and a base resistor. The base circuit transmits DC bias curren...	06/04/2009
20090100307	SYSTEMS AND METHODS FOR PROVIDING NONVOLATILE MEMORY MANAGEMENT IN WIRELESS PHONES The present invention is related to memory management, and in particular, to methods and systems for accessing and managing nonvolatile, such as in a wireless phone. A wireless phone memory controller is disclosed that, comprises a first interface circuit configured to ...	04/16/2009
20090096507	Integrated Semiconductor Metal-Insulator-Semiconductor Capacitor An integrated MIS capacitor has two substantially identical MIS capacitors. A first capacitor comprises a first region of a first conductivity type adjacent to a channel region of the first conductivity type in a semiconductor substrate. The semiconductor substrate has ...	04/16/2009
20090091396	METHOD AND SYSTEM FOR CALIBRATION OF A TANK CIRCUIT IN A PHASE LOCK LOOP A phase lock loop includes a calibration loop for calibrating a tank circuit for capacitance variation through process variations of manufacturing an integrated circuit including the phase lock loop. A capacitance profile for setting the frequency of the phase lock loop...	04/09/2009
20090073770	Independent Bi-Directional Margin Control Per Level And Independently Expandable Reference Cell Levels For Flash Memory Sensing A memory system includes reference level generators that may provide programmable margins, and programmable verify voltage levels. The reference levels may be shifted within a range of voltages with varying differences between reference voltage levels and with different...	03/19/2009
20090067239	FLASH MEMORY ARRAY SYSTEM INCLUDING A TOP GATE MEMORY CELL A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. Th...	03/12/2009
20090067235	Test circuit and method for multilevel cell flash memory A test device and method may be used to detect voltage, current or signals of a digital multilevel memory cell system or to test operation or performance by applying inputted voltages, currents or signals to the memory cell system....	03/12/2009
20090061547	Landing Pad for Use As a Contact to a Conductive Spacer A landing pad for use as a contact to a conductive spacer adjacent a structure in a semiconductor device comprises two islands, each of which is substantially rectangularly shaped and is spaced apart from one another and from the structure. Conductive spacers are adjace...	03/05/2009
20090052248	FLASH MEMORY ARRAY SYSTEM INCLUDING A TOP GATE MEMORY CELL A memory system includes memory cells arranged in sectors. A decoder corresponding to a sector disables memory cells having a defective top gate. The decoder may include a low voltage or high voltage latch for the disabling. A top gate handling algorithm is included. Th...	02/26/2009
20090023413	Cross Coupled High Frequency Buffer A local oscillator (LO) buffer circuit comprises first and second LO buffers arranged in a cross coupled configuration. The first LO buffer generates in-phase output signals in response to in-phase input signals, and quadrature output signals from the second LO buffer. ...	01/22/2009
20090016113	NON-DIFFUSION JUNCTION SPLIT-GATE NONVOLATILE MEMORY CELLS AND ARRAYS, METHODS OF PROGRAMMING, ERASING, AND READING THEREOF, AND METHODS OF MANUFACTURE Nonvolatile flash memory systems and methods are disclosed having a semiconductor substrate of a first conductivity type, including non-diffused channel regions through which electron flow is induced by application of voltage to associated gate elements. A plurality of ...	01/15/2009
20090016106	SUB VOLT FLASH MEMORY SYSTEM Various circuits include MOS transistors that have a bulk voltage terminal for receiving a bulk voltage that is different from a supply voltage and ground. The bulk voltage may be selectively set so that some MOS transistors have a bulk voltage set to the supply voltage...	01/15/2009
20090004807	PASSIVE ELEMENTS, ARTICLES, PACKAGES, SEMICONDUCTOR COMPOSITES, AND METHODS OF MANUFACTURING SAME Systems and methods associated with semiconductor articles are disclosed, including forming a first layer of material on a substrate, etching trenches within regions defining a passive element in the first layer, forming metal regions on sidewalls of the trenches, and f...	01/01/2009

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Assignee: Silicon Storage Technology, Inc.