Assignee: Rambus Inc.

Location: Los Altos, CA, US
No. of applications: 124

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Application No.	Application Title	Issue Date
20120082203	SELECTABLE-TAP EQUALIZER A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a fi...	04/05/2012
20120081146	SIGNAL LINES WITH INTERNAL AND EXTERNAL TERMINATION Embodiments of a memory controller are described. This memory controller communicates signals to a memory device via a signal line, which can be a data signal line or a command/address signal line. Termination of the signal line is divided between an external impedance ...	04/05/2012
20120030420	PROTOCOL FOR REFRESH BETWEEN A MEMORY CONTROLLER AND A MEMORY DEVICE The present embodiments provide a system that supports self-refreshing operations in a memory device. During operation, the system transitions the memory device from an auto-refresh state, wherein a memory controller controls refreshing operations for the memory device,...	02/02/2012
20120023363	PROTOCOL INCLUDING A COMMAND-SPECIFIED TIMING REFERENCE SIGNAL Apparatus and methods for operation of a memory controller, memory device and system are described. During operation, the memory controller transmits a read command which specifies that a memory device output data accessed from a memory core. This read command contains ...	01/26/2012
20110264849	PROTOCOL INCLUDING TIMING CALIBRATION BETWEEN MEMORY REQUEST AND DATA TRANSFER The described embodiments provide a system for controlling an integrated circuit memory device by a memory controller. During operation, the system sends a memory-access request from the memory controller to the memory device using a first link. After sending the memory...	10/27/2011
20120011331	MEMORY SYSTEM, CONTROLLER AND DEVICE THAT SUPPORTS A MERGED MEMORY COMMAND PROTOCOL The present embodiments provide a memory system which is configured to send a request from a memory controller to a memory device, wherein the request includes independent activate and precharge commands. The activate command is associated with a row address, which iden...	01/12/2012
20110307672	MEMORY INTERFACE WITH INTERLEAVED CONTROL INFORMATION A memory system communicates at least partially temporally overlapping write-data sequences associated with independent column write accesses on data links from a memory controller to a memory device via bidirectional links. Each of these write-data sequences may be ass...	12/15/2011
20110291693	TESTING FUSE CONFIGURATIONS IN SEMICONDUCTOR DEVICES Methods, systems, and apparatus for testing semiconductor devices. A semiconductor device includes one or more external terminals configured to receive fuse configuration data from an external source. The semiconductor device also includes a soft-blow circuit to generat...	12/01/2011
20110289510	ATOMIC-OPERATION COALESCING TECHNIQUE IN MULTI-CHIP SYSTEMS A cache-coherence protocol distributes atomic operations among multiple processors (or processor cores) that share a memory space. When an atomic operation that includes an instruction to modify data stored in the shared memory space is directed to a first processor tha...	11/24/2011
20110289258	MEMORY INTERFACE WITH REDUCED READ-WRITE TURNAROUND DELAY Embodiments of a memory system that communicates bidirectional data between a memory controller and a memory IC via bidirectional links using half-duplex communication are described. Each of the bidirectional links conveys write data or read data, but not both. States o...	11/24/2011
20110251819	INTEGRATED CIRCUIT TESTING MODULE INCLUDING SIGNAL SHAPING INTERFACE Systems and methods of testing integrated circuits are disclosed. The systems include a test module configured to operate between automated testing equipment and an integrated circuit to be tested. The testing interface is configured to test the integrated circuit at a ...	10/13/2011
20110249718	METHOD AND APPARATUS FOR CORRECTING PHASE ERRORS DURING TRANSIENT EVENTS IN HIGH-SPEED SIGNALING SYSTEMS A system for dynamically correcting phase errors between data and a timing reference signal caused by a transient event during data communication between a transmitter and a receiver is described. During operation, the system stores one or more phase-offset values for t...	10/13/2011
20110239084	CODE-ASSISTED ERROR-DETECTION TECHNIQUE Embodiments of a circuit are described. In this circuit, an encoder circuit encodes a set of N symbols as a given codeword in a code space, where the given codeword includes a set of M symbols. M drivers are coupled to the encoder circuit and are coupled to M links in a...	09/29/2011
20110239063	ACTIVE CALIBRATION FOR HIGH-SPEED MEMORY DEVICES A system for calibrating timing for write operations between a memory controller and a memory device is described. During operation, the system identifies a time gap required to transition from writing data from the memory controller to the memory device to reading data...	09/29/2011
20110235459	CLOCK-FORWARDING LOW-POWER SIGNALING SYSTEM In a low-power signaling system, an integrated circuit device includes an open loop-clock distribution circuit and a transmit circuit that cooperate to enable high-speed transmission of information-bearing symbols unaccompanied by source-synchronous timing references. T...	09/29/2011
20110219197	Memory Controllers, Systems, and Methods Supporting Multiple Request Modes A memory system includes a memory controller with a plurality N of memory-controller blocks, each of which conveys independent transaction requests over external request ports. The request ports are coupled, via point-to-point connections, to from one to N memory device...	09/08/2011
20110216611	METHOD AND APPARATUS FOR CALIBRATING WRITE TIMING IN A MEMORY SYSTEM A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calib...	09/08/2011
20110211403	BIMODAL MEMORY CONTROLLER A memory controller has a communication path which is coupled to an external, wired electrical path. The memory controller includes at least two alternative interface circuits to communicate with the external, wired electrical path using signals having one of two differ...	09/01/2011
20110202789	PROCESSOR-MEMORY UNIT FOR USE IN SYSTEM-IN-PACKAGE AND SYSTEM-IN-MODULE DEVICES An apparatus and method for a processor-memory unit for use in system-in-package (SiP) and system-in-package (SiP) integrated circuit devices. The apparatus includes a processing module, a memory module and a programmable system module. The programmable system module is...	08/18/2011
20110202709	OPTIMIZING STORAGE OF COMMON PATTERNS IN FLASH MEMORY One embodiment of the present invention provides a method of operation within a flash memory system. During operation, the system receives write data and a corresponding logical address. The system then determines whether the write data matches a predetermined data patt...	08/18/2011
20110156776	Locked Loop Circuit With Clock Hold Function A locked loop circuit having a clock hold function. The locked loop circuit includes a select circuit, phase mixing circuit, hold signal generator and latch circuit. The select circuit selects one of a plurality of phase values in response to a select signal, and the ph...	06/30/2011
20110128040	SIGNAL LINES WITH INTERNAL AND EXTERNAL TERMINATION Embodiments of a memory controller are described. This memory controller communicates signals to a memory device via a signal line, which can be a data signal line or a command/address signal line. Termination of the signal line is divided between an external impedance ...	06/02/2011
20110126081	REQUEST-COMMAND ENCODING FOR REDUCED-DATA-RATE TESTING Embodiments of a memory device are described. This memory device includes a signal connector which is electrically coupled to a command/address (CA) link, and an interface circuit, which is electrically coupled to the signal connector, and which receives CA packets via ...	05/26/2011
20110119425	DETACHABLE INTERCONNECT FOR CONFIGURABLE WIDTH MEMORY SYSTEM The disclosure relates to a detachable signalling interconnect apparatus that provides connectivity between two or more components of a memory system in conjunction with different modes of operation of the components. The memory system comprises: a first socket to recei...	05/19/2011
20110102043	REDUCING POWER-SUPPLY-INDUCED JITTER IN A CLOCK-DISTRIBUTION CIRCUIT A system for compensating for power-supply-induced jitter (PSIJ) in a chain of clock buffers within an integrated circuit is described. During operation, the system couples a first supply voltage from a first voltage source to a supply node of each clock buffer in a fir...	05/05/2011
20110066792	Segmentation Of Flash Memory For Partial Volatile Storage This disclosure provides a method and system that segment flash memory to have differently managed regions. More particularly, flash memory is segmented into a “non-volatile” region, where program counts are restricted to preserve baseline retention assumptions, and...	03/17/2011
20110064172	Systems and Methods for Serial Cancellation A receiver in a CDMA system comprises a front end processor that generates a combined signal per source. A symbol estimator processes the combined signal to produce symbol estimates. An S-Matrix Generation module refines these symbol estimates based on the sub channel s...	03/17/2011
20110064066	Methods for Estimation and Interference Cancellation for signal processing A receiver in a CDMA system comprises a front end processor that generates a combined signal per source. A symbol estimator processes the combined signal to produce symbol estimates. An S-Matrix Generation module refines these symbol estimates based on the sub channel s...	03/17/2011
20110060868	MULTI-BANK FLASH MEMORY ARCHITECTURE WITH ASSIGNABLE RESOURCES This disclosure has described embodiments of a nonvolatile memory that includes at least two concurrently accessible memory banks (302), each including nonvolatile memory cells. The nonvolatile memory further includes at least one sharable resource (306), ...	03/10/2011
20110051854	ERROR DETECTION AND OFFSET CANCELLATION DURING MULTI-WIRE COMMUNICATION Embodiments of a circuit are described. In this circuit, a receive circuit includes M input nodes that receive a set of M symbols on M links during a time interval, where the set of M symbols are associated with a codeword. Moreover, the receive circuit includes a decod...	03/03/2011
20110044378	Iterative Interference Canceler for Wireless Multiple-Access Systems with Multiple Receive Antennas This invention teaches to the details of an interference canceling receiver for canceling intra-cell and inter-cell interference in coded, multiple-access, spread spectrum transmissions that propagate through frequency selective communication channels to a multiplicity ...	02/24/2011
20110043220	METHOD AND APPARATUS FOR POWER SEQUENCE TIMING TO MITIGATE SUPPLY RESONANCE IN POWER DISTRIBUTION NETWORK The transient load current of a circuit powered by a power distribution network is increased in a plurality of steps, with the step transition times being adjusted based on the transient noise of the power distribution network. This reduces the resonance noise that woul...	02/24/2011
20110037772	Scalable Unified Memory Architecture A memory architecture includes a memory controller coupled to multiple modules. Each module includes a computing engine coupled to a shared memory. Each computing engine is capable of receiving instructions from the memory controller and processing the received instruct...	02/17/2011
20110029801	Method and System for Balancing Receive-Side Supply Load Described are digital communication systems that transmit and receive parallel sets of data symbols. Differences between successive sets of symbols induce changes in the current used to express the symbol sets, and thus introduce supply ripple. A receiver adds compensat...	02/03/2011
20110025533	ENCODING DATA WITH MINIMUM HAMMING WEIGHT VARIATION M-bit data are encoded into n-bit data such that the encoded n-bit data has a sufficient number of encoded data patterns enough to encode the number (2^m) of data patterns in the m-bit data but that the n-bit data has Hamming Weights (HWs) with minimum (smalle...	02/03/2011
20110019760	Methods and Systems for Reducing Supply and Termination Noise A transmitter expresses continuous-time signals on alternate, parallel channels with reference to different supply voltages such that the signals on alternate channels have different common-mode voltages. At the transmitter, expressing the symbols using alternate supply...	01/27/2011
20110019656	Advanced signal processors for Interference Cancellation in baseband receivers An interference canceller comprises a composite interference vector (CIV) generator configured to produce a CIV by combining soft and/or hard estimates of interference, an interference-cancelling operator configured for generating a soft projection operator, and a soft-...	01/27/2011
20110018599	Partial Response Receiver And Related Method A multi-phase partial response equalizer circuit includes sampler circuits that sample an input signal to generate sampled signals in response to sampling clock signals having different phases. A first multiplexer circuit selects one of the sampled signals as a first sa...	01/27/2011
20110016352	PROGRAMMABLE MEMORY REPAIR SCHEME The present disclosure provides semiconductor devices and methods, systems, and apparatus for testing and operating the same. A semiconductor memory device includes data storage elements and a repair circuit. The data storage elements include primary data storage elemen...	01/20/2011
20110004726	PIECEWISE ERASURE OF FLASH MEMORY Embodiments of a circuit are described. This circuit includes control logic that generates multiple piecewise-erase commands to erase information stored in a storage cell of a memory device formed within another circuit. Note that execution of a single one of the multip...	01/06/2011

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Assignee: Rambus Inc.