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| Application No. | Application Title | Issue Date |
| 20120131267 | MEMORY DEVICE DISTRIBUTED CONTROLLER SYSTEM A memory device distributed controller circuit distributes memory control functions amongst a plurality of memory controllers. A master controller receives an interpreted command and activates the appropriate slave controllers depending on the command. The slave control... | 05/24/2012 |
| 20120127794 | PROGRAM VERIFY OPERATION IN A MEMORY DEVICE Methods for program verifying, program verify circuits, and memory devices are disclosed. One such method for program verifying includes generating a ramped voltage for a plurality of count values. The ramped voltage is applied to a control gate of a memory cell being p... | 05/24/2012 |
| 20120127793 | MEMORY ARRAYS A memory array includes a control gate, where every memory cell coupled to a first side of the control gate is within a first row of memory cells and every memory cell coupled to a second side of the control gate is within a second row of memory cells, and where the fir... | 05/24/2012 |
| 20120110375 | MACRO AND COMMAND EXECUTION FROM MEMORY ARRAY Methods and apparatus for executing internal operations of memory devices utilizing instructions stored in the memory array of the memory device are disclosed. Decode blocks adapted to interpret instructions and data stored in the memory device are also disclosed. Metho... | 05/03/2012 |
| 20120108042 | Methods Of Forming Doped Regions In Semiconductor Substrates Some embodiments include methods of forming one or more doped regions in a semiconductor substrate. Plasma doping may be used to form a first dopant to a first depth within the substrate. The first dopant may then be impacted with a second dopant to knock the first dopa... | 05/03/2012 |
| 20120106261 | SYSTEMS AND METHODS FOR ERASING A MEMORY Methods of erasing a memory, methods of operating a memory, memory devices, and systems. In one such method, an erase block is erased to an intermediate erase voltage before it is erased to a final erase voltage, such as to tighten an erase distribution. Faster erasing ... | 05/03/2012 |
| 20120106249 | PROGRAMMING ERROR CORRECTION CODE INTO A SOLID STATE MEMORY DEVICE WITH VARYING BITS PER CELL Memory devices that, in a particular embodiment, receive and transmit analog data signals representative of bit patterns of two or more bits such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bi... | 05/03/2012 |
| 20120084494 | MEMORY FOR ACCESSING MULTIPLE SECTORS OF INFORMATION SUBSTANTIALLY CONCURRENTLY A memory storage system of an embodiment includes a non-volatile memory unit and memory control circuitry coupled to the memory unit. The memory control circuitry is configured to access multiple sectors of information substantially concurrently.... | 04/05/2012 |
| 20120084493 | NON-VOLATILE MEMORY DEVICE HAVING ASSIGNABLE NETWORK IDENTIFICATION Memory devices and methods disclosed such as a memory device having a plurality of memory dies where each die includes a network identification that uniquely identifies the memory die on a bus. Access for each memory die to the bus can be scheduled by a bus controller.... | 04/05/2012 |
| 20120081972 | MEMORY ARRAYS AND METHODS OF OPERATING MEMORY Apparatus and methods for determining pass/fail condition of memories are disclosed. In at least one embodiment, a set of common lines, one for each rank of page buffers corresponding to a page, determine the pass/fail status of all connected memory cells, and the pass/... | 04/05/2012 |
| 20120081968 | N WELL IMPLANTS TO SEPARATE BLOCKS IN A FLASH MEMORY DEVICE A semiconductor memory device that has an isolated area formed from one conductivity and formed in part by a buried layer of a second conductivity that is implanted in a substrate. The walls of the isolated area are formed by implants that are formed from the second con... | 04/05/2012 |
| 20120072653 | MEMORY DEVICE WITH USER CONFIGURABLE DENSITY/PERFORMANCE The memory device is comprised of a memory array having a plurality of memory cells that are organized into memory blocks. Each memory cell is capable of storing a selectable quantity of data bits (e.g., multiple level cells or a single bit per cell). Control circuitry ... | 03/22/2012 |
| 20120069680 | NAND WITH BACK BIASED OPERATION Methods of programming, reading and erasing memory cells are disclosed. In at least one embodiment, program, sense, and erase operations in a memory are performed with back biased operation, such as to improve high voltage device isolation and cutoff in string drivers a... | 03/22/2012 |
| 20120051161 | MEMORY DEVICES AND METHODS OF OPERATING MEMORY Methods and apparatus for synchronizing a delay locked loop, such as delay locked loops used with NAND memories are disclosed. In at least one embodiment, one or both of a clock and the delay locked loop are stopped for energy savings. A synchronization start signal can... | 03/01/2012 |
| 20120051139 | REDUCING READ FAILURE IN A MEMORY DEVICE Read failure is reduced by increasing the drain current through a serial string of memory cells during the read operation. In one embodiment, this is accomplished by using a higher read pass voltage for unselected word lines when the selected word line is within a prede... | 03/01/2012 |
| 20120049248 | TRANSISTORS HAVING A CONTROL GATE AND ONE OR MORE CONDUCTIVE STRUCTURES Transistors having a dielectric over a semiconductor, a control gate over the dielectric at a particular level, and one or more conductive structures over the dielectric at the particular level facilitate control of device characteristics of the transistor. The one or m... | 03/01/2012 |
| 20120049245 | MEMORY ARRAY WITH AN AIR GAP BETWEEN MEMORY CELLS AND THE FORMATION THEREOF Memory arrays and their formation are disclosed. One such memory array has first and second memory cells over a semiconductor, an air gap between the first and second memory cells, and an isolation region within the semiconductor and under the air gap so that the isolat... | 03/01/2012 |
| 20120044769 | MULTI-PASS PROGRAMMING IN A MEMORY DEVICE A method for programming a memory device, a memory device, and a memory system are provided. According to at least one such method, a first programming pass generates a plurality of first programming pulses to increase the threshold voltages of target memory cells to ei... | 02/23/2012 |
| 20120044768 | PROGRAMMING TO MITIGATE MEMORY CELL PERFORMANCE DIFFERENCES Methods for programming and memory devices are disclosed. In one such method for programming, a first programming voltage applied to control gates of a group of memory cells generates a maximum threshold voltage of the group of memory cell threshold voltages. A voltage ... | 02/23/2012 |
| 20120044765 | WORD LINE ACTIVATION IN MEMORY DEVICES Memory devices and methods are disclosed, such as those facilitating flexibility in applying differing biasing schemes to word lines. For example, one such memory device can include an architecture capable of partitioning word lines into one of a plurality of address sp... | 02/23/2012 |
| 20120044742 | VARIABLE RESISTANCE MEMORY ARRAY ARCHITECTURE Memory devices, memory arrays, and methods of operation of memory arrays are disclosed. In one such memory device, a parallel selection architecture includes a control element, such as a selection transistor, in parallel with a variable resistance memory cell. Biasing o... | 02/23/2012 |
| 20120043661 | INTEGRATED CIRCUITS AND METHODS OF FORMING CONDUCTIVE LINES AND CONDUCTIVE PADS THEREFOR Integrated circuits and methods for forming conductive lines and conductive pads of integrated circuits are disclosed. One such integrated circuit includes circuitry, a first conductor coupled to the circuitry, a conductive pad coupled to the first conductor, and a seco... | 02/23/2012 |
| 20120042148 | LINE TERMINATION METHODS AND APPARATUS Methods and apparatus for termination of signal lines coupled to a number of memory devices are disclosed. One such method includes adjusting an input impedance of one or more terminals of an interface of a memory device in response to the memory device receiving a part... | 02/16/2012 |
| 20120033504 | ERASE VOLTAGE REDUCTION IN A NON-VOLATILE MEMORY DEVICE In erasing a memory block of memory cells, a semiconductor tub that contains a memory block to be erased can be biased with a high, positive voltage. The control gates of the memory cells that make up the memory block can be biased with a negative voltage. An erase veri... | 02/09/2012 |
| 20120030529 | REFRESH OF NON-VOLATILE MEMORY CELLS BASED ON FATIGUE CONDITIONS In one or more of the disclosed embodiments, memory cells in a memory device are refreshed upon an indication of a fatigue condition. In one such embodiment, controller monitors behavior parameters of the cells and determines if any of the parameters are outside of a no... | 02/02/2012 |
| 20120026816 | DEFECTIVE MEMORY BLOCK IDENTIFICATION IN A MEMORY DEVICE During manufacture and testing of a memory device, a memory test is performed to determine which, if any, memory blocks are defective. A memory map of the defective blocks is stored in one of the defect-free memory blocks so that it can be read later by a controller dur... | 02/02/2012 |
| 20120026792 | ERASE CYCLE COUNTER USAGE IN A MEMORY DEVICE Memory devices to facilitate adjustment of program voltages applied during a program operation based upon erase operation cycle counter values stored in the memory device. In one such embodiment, an erase cycle counter is maintained for each block of a memory device and... | 02/02/2012 |
| 20110280078 | CHARGE PUMP OPERATION IN A NON-VOLATILE MEMORY DEVICE A charge pump in a memory device is activated to produce a programming voltage prior to data loading during a programming operation. During an initial programming cycle, first and second load voltages are charged from the charge pump. The first load is removed from the ... | 11/17/2011 |
| 20110280077 | MULTI-SEMICONDUCTOR MATERIAL VERTICAL MEMORY STRINGS, STRINGS OF MEMORY CELLS HAVING INDIVIDUALLY BIASABLE CHANNEL REGIONS, MEMORY ARRAYS INCORPORATING SUCH STRINGS, AND METHODS OF ACCESSING AND FORMING THE SAME Multi-semiconductor vertical memory strings, strings of memory cells having individually biasable channel regions, arrays incorporating such strings and methods for forming and accessing such strings are provided. For example non-volatile memory devices are disclosed th... | 11/17/2011 |
| 20110275182 | STACKED NON-VOLATILE MEMORY WITH SILICON CARBIDE-BASED AMORPHOUS SILICON THIN FILM TRANSISTORS A stacked non-volatile memory device uses amorphous silicon based thin film transistors stacked vertically. Each layer of transistors or cells is formed from a deposited a-Si channel region layer having a predetermined concentration of carbon to form a carbon rich silic... | 11/10/2011 |
| 20110273940 | LEVEL SHIFTING CIRCUIT A level shifting circuit having an input and an output where the level shifting circuit is configured to receive a logical high level having a first voltage level at the input and to output a logical high level having a second voltage level at the output where the secon... | 11/10/2011 |
| 20110273933 | ANALOG-TO-DIGITAL AND DIGITAL-TO-ANALOG CONVERSION WINDOW ADJUSTMENT BASED ON REFERENCE CELLS IN A MEMORY DEVICE An analog-to-digital conversion window is defined by reference voltages stored in reference memory cells of a memory device. A first reference voltage is read to define an upper limit of the conversion window and a second reference voltage is read to define a lower limi... | 11/10/2011 |
| 20110273931 | METHODS OF OPERATING MEMORY CELL HAVING ASYMMETRIC BAND-GAP TUNNEL INSULATOR USING DIRECT TUNNELING Methods of operating dual-gate memory cells having asymmetric band-gap tunnel insulators using direct tunneling. The asymmetric band-gap tunnel insulators allow for low voltage direct tunneling programming and efficient erase with holes and/or electrons, while maintaini... | 11/10/2011 |
| 20110273929 | SEMICONDUCTOR MAGNETIC MEMORY INTEGRATING A MAGNETIC TUNNELING JUNCTION ABOVE A FLOATING-GATE MEMORY CELL A semiconductor magnetic memory device has a magnetic tunneling junction formed over a memory cell. The memory cell has a control gate surrounded by a floating gate. The floating gate is coupled to the magnetic tunneling junction through a pinning layer that maintains t... | 11/10/2011 |
| 20110273219 | VOLTAGE SWITCHING IN A MEMORY DEVICE Voltage switches, memory devices, memory systems, and methods for switching are disclosed. One such voltage switch uses a pair of switch circuits coupled in series, each switch circuit being driven by a level shift circuit. Each switch circuit uses a group of series cou... | 11/10/2011 |
| 20110272754 | MEMORIES AND THEIR FORMATION Memories and their formation are disclosed. One such memory has a first array of first memory cells extending in a first direction from a first surface of a semiconductor. A second array of second memory cells extends in a second direction, opposite to the first directi... | 11/10/2011 |
| 20110267882 | MEMORY ARRAY WITH INVERTED DATA-LINES PAIRS At least one data-line pair has a first data line aligned with a first column of memory cells and a second data line aligned with a second column of memory cells. The first data line is coupled to the second column of memory cells and the second data line is coupled to ... | 11/03/2011 |
| 20110261624 | DATA LINE MANAGEMENT IN A MEMORY DEVICE Methods for programming a memory device, memory devices configured to perform the disclosed programming methods, and memory systems having a memory device configured to perform the disclosed programming methods are provided. According to at least one such method, multip... | 10/27/2011 |
| 20110261607 | Arrays Of Vertically Stacked Tiers Of Non-Volatile Cross Point Memory Cells, Methods Of Forming Arrays Of Vertically Stacked Tiers Of Non-Volatile Cross Point Memory Cells, And Methods Of Reading A Data Value Stored By An Array Of Vertically Stacked Tiers Of Non-Volatile Cross Point Memory Cells An array of vertically stacked tiers of non-volatile cross point memory cells includes a plurality of horizontally oriented word lines within individual tiers of memory cells. A plurality of horizontally oriented global bit lines having local vertical bit line extension... | 10/27/2011 |
| 20120012921 | MEMORY ARRAYS HAVING SUBSTANTIALLY VERTICAL, ADJACENT SEMICONDUCTOR STRUCTURES AND THE FORMATION THEREOF Memory arrays and methods of their formation are disclosed. One such memory array has memory-cell strings are formed adjacent to separated substantially vertical, adjacent semiconductor structures, where the separated semiconductor structures couple the memory cells of ... | 01/19/2012 |
