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...Daniel Webster invented a "bull plow" to pull out tree stumps. It didn't catch on because it was huge and required four oxen to pull it!
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| Application No. | Application Title | Issue Date |
| 20130051142 | MEMORY WITH THREE TRANSISTOR MEMORY CELL DEVICE Memory, memory devices, and a method for a backup sequence are disclosed. In one such memory device, sense circuitry and page buffers are coupled between a three transistor memory cell device and a non-volatile memory device. Enable/disable gates enable selective access... | 02/28/2013 |
| 20130039138 | METHODS FOR PROVIDING REDUNDANCY AND APPARATUSES Methods for providing redundancy and apparatuses are disclosed. One such method for providing redundancy performs a mapping of data between an address of a memory determined to indicate a defective memory cell and an address of a redundant area of the memory, only after... | 02/14/2013 |
| 20130039129 | MEMORY DEVICES AND CONFIGURATION METHODS FOR A MEMORY DEVICE Memory devices and methods of operating memory devices are disclosed. In one such method, different blocks of memory cells have different configurations of user data space and overhead data space. In at least one method, overhead data is distributed within more than one... | 02/14/2013 |
| 20130036253 | WEAR LEVELING FOR A MEMORY DEVICE Memory devices and methods to facilitate wear leveling operations in a memory device. In one such method, particular blocks of memory cells are excluded from experiencing wear leveling operations performed on the memory device. In at least one method, a user selects blo... | 02/07/2013 |
| 20130033939 | FUNCTIONAL DATA PROGRAMMING AND READING IN A MEMORY Methods for functional programming memory cells and apparatuses are disclosed. One such method for functional programming includes encoding a group of data with a function to generate representative data and programming the representative data to the memory. In one embo... | 02/07/2013 |
| 20130028022 | DYNAMIC PROGRAM WINDOW DETERMINATION IN A MEMORY DEVICE Methods for determining a program window and memory devices are disclosed. One such method for determining the program window measures an amount of program disturb experienced by a particular state and determines the program window responsive to the amount of program di... | 01/31/2013 |
| 20130028017 | DETERMINING AND TRANSFERRING DATA FROM A MEMORY ARRAY Apparatus and methods of operating memory devices are disclosed. In one such method, a first portion of the data states of memory cells are determined and transferred from a memory device while continuing to determine remaining portions of data states of the same memory... | 01/31/2013 |
| 20130027651 | BARRIERS FOR REFLECTIVE PIXEL ELECTRODES OF DISPLAY DEVICES AND METHODS In one or more embodiments, barriers for reflective pixels electrodes of display devices and methods are disclosed. In one such embodiment, a reflective spatial light modulator for a display device has a plurality of reflective pixel electrodes. Each reflective pixel el... | 01/31/2013 |
| 20130026600 | FORMING AIR GAPS IN MEMORY ARRAYS AND MEMORY ARRAYS WITH AIR GAPS THUS FORMED Methods of forming air gaps in memory arrays and memory arrays with air gaps thus formed are disclosed. One such method may include forming an isolation region, having a first dielectric, through a charge-storage structure that is over a semiconductor, the isolation reg... | 01/31/2013 |
| 20130010542 | PROGRAMMING METHODS AND MEMORIES Methods of programming a memory and memories are disclosed. In at least one embodiment, a memory is programmed by determining a pretarget threshold voltage for a selected cell, wherein the pretarget threshold voltage is determined using pretarget threshold voltage value... | 01/10/2013 |
| 20130010540 | PROGRAMMING METHODS FOR A MEMORY DEVICE Methods for programming, memory devices, and memory systems are disclosed. In one such method for programming, a target memory cell is partially programmed to a final target programmed state where the partial programming is verified by applying a ramped voltage having a... | 01/10/2013 |
| 20130010537 | DEVICES AND METHODS OF PROGRAMMING MEMORY CELLS Devices and methods of programming memory cells, both SLC and MLC, such as to reduce charge-storage structure to charge-storage structure coupling, are shown and described. Programming of memory cells can include comparing a first page of data to a second page of data, ... | 01/10/2013 |
| 20130007355 | DATA CONDITIONING TO IMPROVE FLASH MEMORY RELIABILITY Methods and apparatus for managing data storage in memory devices utilizing memory arrays of varying density memory cells. Data can be initially stored in lower density memory. Data can be further read, compacted, conditioned and written to higher density memory as back... | 01/03/2013 |
| 20130003465 | LOCAL SENSING IN A MEMORY DEVICE Methods for sensing, memory devices, and memory systems are disclosed. In one such memory device, a local sense circuit provides sensing of an upper group of memory cells while a global sense circuit provides sensing of a lower group of memory cells. Data sensed by the ... | 01/03/2013 |
| 20130003458 | NAND ARCHITECTURE MEMORY WITH VOLTAGE SENSING A NAND architecture non-volatile memory voltage sensing data read/verify process and sense amplifier has been described that senses data in floating gate or floating node field effect transistor memory cells using a voltage sensing data read/verify process. The voltage ... | 01/03/2013 |
| 20130003456 | SCALABLE MULTI-FUNCTIONAL AND MULTI-LEVEL NANO-CRYSTAL NON-VOLATILE MEMORY DEVICE A multi-functional and multi-level memory cell comprises a tunnel layer formed over a substrate. In one embodiment, the tunnel layer comprises two layers such as HfO2 and LaAlO3. A charge blocking layer is formed over the tunnel layer. In one embod... | 01/03/2013 |
| 20130003451 | REFRESH ARCHITECTURE AND ALGORITHM FOR NON-VOLATILE MEMORIES Methods and systems to refresh a non-volatile memory device, such as a phase change memory. In an embodiment, as a function of system state, a memory device performs either a first refresh of memory cells using a margined read reference level or a second refresh of erro... | 01/03/2013 |
| 20130001671 | SELECT GATES FOR MEMORY Methods of forming memory and memory devices are disclosed, such as a memory device having a memory cell with a floating gate formed from a first conductor, a control gate formed from a second conductor, and a dielectric interposed between the floating gate and the cont... | 01/03/2013 |
| 20120331217 | MEMORY DEVICE PROGRAM WINDOW ADJUSTMENT In one or more embodiments, a memory device has an adjustable programming window with a plurality of programmable levels. The programming window is moved to compensate for changes in reliable program and erase thresholds achievable as the memory device experiences facto... | 12/27/2012 |
| 20120320684 | METHOD FOR DISCHARGING A VOLTAGE FROM A CAPACITANCE IN A MEMORY DEVICE In discharging a voltage from a circuit capacitance, a supply voltage to a memory device is monitored. The capacitance is discharged through a discharge circuit from a relatively high voltage to a relatively low voltage when the supply voltage decreases below a trip vol... | 12/20/2012 |
| 20120314503 | COARSE AND FINE PROGRAMMING IN A SOLID STATE MEMORY Memory devices adapted to receive and transmit analog data signals representative of bit patterns of two or more bits facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. Programming of such memory dev... | 12/13/2012 |
| 20120314171 | DISPLAY DEVICES HAVING ELECTROLESSLY PLATED CONDUCTORS AND METHODS In one or more embodiments, display devices having electrolessly plated conductors and methods are disclosed. One such embodiment is directed to a method of forming a reflective pixel array for a display device, including forming a plurality of conductive pads, each of ... | 12/13/2012 |
| 20120313097 | FLASH MEMORY DEVICE HAVING A GRADED COMPOSITION, HIGH DIELECTRIC CONSTANT GATE INSULATOR A graded composition, high dielectric constant gate insulator is formed between a substrate and floating gate in a flash memory cell transistor. The gate insulator comprises amorphous germanium or a graded composition of germanium carbide and silicon carbide. If the com... | 12/13/2012 |
| 20120311415 | METHOD AND DEVICE FOR DETECTING POSSIBLE CORRUPTION OF SECTOR PROTECTION INFORMATION OF A NON-VOLATILE MEMORY STORED IN AN ON BOARD VOLATILE MEMORY ARRAY AT POWER-ON A non-volatile memory device includes addressable sectors and an ancillary volatile memory array. The ancillary volatile memory array stores protection information in the addressable sectors that is not accessible to users of the memory. The protection information is do... | 12/06/2012 |
| 20120311293 | DYNAMIC MEMORY CACHE SIZE ADJUSTMENT IN A MEMORY DEVICE Methods for dynamic memory cache size adjustment, enabling dynamic memory cache size adjustment, memory devices, and memory systems are disclosed. One such method for dynamic memory cache size adjustment determines available memory space in a memory array and adjusts a ... | 12/06/2012 |
| 20120307576 | ANALOG SENSING OF MEMORY CELLS WITH A SOURCE FOLLOWER DRIVER IN A SEMICONDUCTOR MEMORY DEVICE Memory devices, methods, and sample and hold circuits are disclosed, including a memory device that includes a sample and hold circuit coupled to a bit line. One such sample and hold circuit includes a read circuit, a verify circuit, and a reference circuit. The read ci... | 12/06/2012 |
| 20120294088 | MEMORY SEGMENT ACCESSING IN A MEMORY DEVICE Bit lines of a memory segment are read at substantially the same time by coupling a selected memory segment and, at some of the data lines of any intervening segments, to respective data caches. The bit lines of the unselected memory segments that are not used to couple... | 11/22/2012 |
| 20120294085 | MULTI-PARTITION ARCHITECTURE FOR MEMORY A multiple partition memory and architecture for concurrent operations reduces circuit overhead by providing a common read sense amplifier and program path for multiple partitions. Long separate datalines for read and algorithm operations allow concurrent operation and ... | 11/22/2012 |
| 20120287726 | ARCHITECTURE AND METHOD FOR MEMORY PROGRAMMING Methods of programming a memory, memory devices, and systems are disclosed, for example. In one such method, each data line of a memory to be programmed is biased differently depending upon whether one or more of the data lines adjacent the data line are inhibited. In o... | 11/15/2012 |
| 20120287718 | PROGRAMMING MEMORY CELLS Methods for programming, memory devices, and methods for reading are disclosed. One such method for programming a memory device (e.g., an SLC memory device) includes encoding a two level data stream to a three level stream prior to programming the memory.... | 11/15/2012 |
| 20120284454 | SOLID STATE STORAGE DEVICE CONTROLLER WITH PARALLEL OPERATION MODE A master memory controller comprises a plurality of memory communication channels. At least one of the memory communication channels is used to communicate with one or more slave memory controllers. The master and slave memory controllers can operate in a parallel opera... | 11/08/2012 |
| 20120281480 | SENSING OPERATIONS IN A MEMORY DEVICE Methods for sensing, method for programming, memory devices, and memory systems are disclosed. In one such method for sensing, a counting circuit generates a count output and a translated count output. The count output is converted into a time varying voltage that biase... | 11/08/2012 |
| 20120281474 | DATA LINE MANAGEMENT IN A MEMORY DEVICE Methods for programming a memory device, memory devices configured to perform the disclosed programming methods, and memory systems having a memory device configured to perform the disclosed programming methods are provided. According to at least one such method, multip... | 11/08/2012 |
| 20120280306 | ONE-TRANSISTOR COMPOSITE-GATE MEMORY One-transistor memory devices facilitate nonvolatile data storage through the manipulation of oxygen vacancies within a trapping layer of a field-effect transistor (FET), thereby providing control and variation of threshold voltages of the transistor. Various threshold ... | 11/08/2012 |
| 20120275233 | SOFT LANDING FOR DESIRED PROGRAM THRESHOLD VOLTAGE Methods of programming memory cells are disclosed. In at least one embodiment, programming is accomplished by applying a first set of programming pulses to program to an initial threshold voltage, and applying a second set of programming pulses to program to a final thr... | 11/01/2012 |
| 20120275227 | PHOTOSENSITIVE COMPOSITION AND COMPOUND FOR USE IN THE PHOTOSENESITIVE COMPOSITION A programming method and memory structure for preventing punch-through in a short channel source-side select gate structure includes adjusting voltages on the selected and unselected bitlines, and the program, pass, and select gate voltages.... | 11/01/2012 |
| 20120274376 | DUTY CYCLE CORRECTOR CIRCUITS Duty cycle corrector circuits that utilize differing unit delay elements in their delay lines in either a graduated or a stepped unit time delay arrangement are for synchronizing with a clock signal. These graduated or a stepped unit time delays allow reduction in the n... | 11/01/2012 |
| 20120273870 | MEMORY ARRAYS HAVING SUBSTANTIALLY VERTICAL, ADJACENT SEMICONDUCTOR STRUCTURES AND THE FORMATION THEREOF Memory arrays and methods of their formation are disclosed. One such memory array has memory-cell strings are formed adjacent to separated substantially vertical, adjacent semiconductor structures, where the separated semiconductor structures couple the memory cells of ... | 11/01/2012 |
| 20120271974 | SATA MASS STORAGE DEVICE EMULATION ON A PCIe INTERFACE A mass storage device, system, and method for operating a mass storage device are disclosed. In one such mass storage device, a host bus adaptor emulates a SATA mass storage device over a PCIe interface with a host system. The host system generates commands with the PCI... | 10/25/2012 |
| 20120269004 | MULTIPLE LEVEL PROGRAM VERIFY IN A MEMORY DEVICE A series of programming pulses are applied to a memory cell to be programmed. A program verify pulse, at an initial program verify voltage, is applied to the memory cell after each programming pulse. The initial program verify voltage is a verify voltage that has been i... | 10/25/2012 |
